AS4C4M32S-7TCN

AS4C4M32S-7TCN Datasheet

AS4C4M32S

Part	Datasheet
AS4C4M32S-7TCN	AS4C4M32S-7TCN (pdf)

Related Parts	Information
AS4C4M32S-6TCN	AS4C4M32S-6TCN
AS4C4M32S-7TCNTR	AS4C4M32S-7TCNTR
AS4C4M32S-6TCNTR	AS4C4M32S-6TCNTR
AS4C4M32S-6TIN	AS4C4M32S-6TIN
AS4C4M32S-6TINTR	AS4C4M32S-6TINTR

PDF Datasheet Preview
AS4C4M32S 4M x 32 bit Synchronous DRAM SDRAM Alliance Memory Confidential • Clock rate 143/166 MHz • Fully synchronous operation • Internal pipelined architecture • 1M word x 32-bit x 4-bank • Programmable Mode - CAS Latency 2, or 3 - Burst Length 1, 2, 4, 8, or full page - Burst Type Sequential & Interleave - Burst-Read-Single-Write - Burst stop function • Individual byte controlled by DQM0-3 • Operating temperature range • Commercial 0 ~ 70°C • Industrial -40 ~ 85°C • Auto Refresh and Self Refresh • 4096 refresh cycles/64ms • Single 3.3V power supply • Interface LVTTL • 86-pin 400 mil plastic TSOP II package - Pb free and Halogen free Overview The AS4C4M32S SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as a quad 1M x 32 DRAM with a synchronous interface all signals are registered on the positive edge of the clock signal, CLK . Each of the 1M x 32 bit banks is organized as 4096 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The AS4C4M32S provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth. Table Key Specifications AS4C4M32S tCK3 Clock Cycle time min. tAC3 Access time from CLK max. tRAS Row Active time min. tRC Row Cycle time min. Table Ordering Information -6/7 6/7ns ns 42 ns 60 ns Part Number Frequency Package AS4C4M32S-7TCN 143MHz 86 pin TSOP II AS4C4M32S-6TCN 166MHz 86 pin TSOP II AS4C4M32S-6TIN 166MH] 86 pin TSOP II T indicates TSOP II package C indicates Commercial temp. I indicates Industrial temp N indicates lead free Figure Pin Assignment Top View VDDQ DQ1 4 DQ2 5 VSSQ DQ3 7 DQ4 8 VDDQ DQ5 10 DQ6 11 VSSQ DQ7 13 NC 14 DQM0 16 CAS# RAS# A11 21 BS0 22 BS1 23 A10/AP 24 A0 25 A1 26 A2 27 DQM2 28 NC 30 DQ16 31 VSSQ 32 DQ17 33 DQ18 34

PDF Datasheet Preview

AS4C4M32S
4M x 32 bit Synchronous DRAM SDRAM

Alliance Memory Confidential
• Clock rate 143/166 MHz
• Fully synchronous operation
• Internal pipelined architecture
• 1M word x 32-bit x 4-bank
• Programmable Mode
- CAS Latency 2, or 3 - Burst Length 1, 2, 4, 8, or full page - Burst Type Sequential & Interleave - Burst-Read-Single-Write - Burst stop function
• Individual byte controlled by DQM0-3
• Operating temperature range
• Commercial 0 ~ 70°C
• Industrial -40 ~ 85°C
• Auto Refresh and Self Refresh
• 4096 refresh cycles/64ms
• Single 3.3V power supply
• Interface LVTTL
• 86-pin 400 mil plastic TSOP II package - Pb free and Halogen free

Overview

The AS4C4M32S SDRAM is a high-speed CMOS synchronous DRAM containing 128 Mbits. It is internally configured as a quad 1M x 32 DRAM with a synchronous interface all signals are registered on the positive edge of the clock signal, CLK . Each of the 1M x 32 bit banks is organized as 4096 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.

The AS4C4M32S provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use.

By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth.

Table Key Specifications

AS4C4M32S tCK3 Clock Cycle time min. tAC3 Access time from CLK max. tRAS Row Active time min. tRC Row Cycle time min.
Table Ordering Information
-6/7 6/7ns ns 42 ns 60 ns

Part Number Frequency Package

AS4C4M32S-7TCN
143MHz 86 pin TSOP II

AS4C4M32S-6TCN
166MHz 86 pin TSOP II

AS4C4M32S-6TIN
166MH] 86 pin TSOP II

T indicates TSOP II package

C indicates Commercial temp. I indicates Industrial temp

N indicates lead free

Figure Pin Assignment Top View

VDDQ

DQ1 4

DQ2 5

VSSQ

DQ3 7

DQ4 8

VDDQ

DQ5 10

DQ6 11

VSSQ

DQ7 13

NC 14

DQM0 16

CAS#

RAS#

A11 21

BS0 22

BS1 23

A10/AP 24

A0 25

A1 26

A2 27

DQM2 28

NC 30

DQ16 31

VSSQ 32

DQ17 33

DQ18 34

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AS4C4M32S-7TCN Datasheet file may be downloaded here without warranties.

Datasheet ID: AS4C4M32S-7TCN 516134