A3958SLBTR-T

A3958SLBTR-T Datasheet

A3958 DMOS Full-Bridge PWM Motor Driver

Part	Datasheet
A3958SLBTR-T	A3958SLBTR-T (pdf)

Related Parts	Information
A3958SB	A3958SB
A3958SB-T	A3958SB-T
A3958SLB	A3958SLB
A3958SLB-T	A3958SLB-T
A3958SLBTR	A3958SLBTR

PDF Datasheet Preview
A3958 DMOS Full-Bridge PWM Motor Driver ±2 A, 50 V continuous output rating Low rDS on outputs 270 mΩ, typical Programmable mixed, fast, and slow current-decay modes Serial interface controls chip functions Synchronous rectification for low power dissipation Internal UVLO and thermal-shutdown circuitry Crossover-current protection Packages: Package B, 24-pin DIP with exposed tabs Not to scale Package LB, 24-pin SOIC with internally fused pins Designed for pulse width modulated PWM current control of DC motors, the A3958 is capable of continuous output currents to ±2 A and operating voltages to 50 V. Internal fixed off-time PWM current-control timing circuitry can be programmed via a serial interface to operate in slow, fast, and mixed currentdecay modes. PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a DC motor with externally applied PWM-control signals. The ENABLE input can be programmed via the serial port to PWM the bridge in fast or slow current decay. Internal synchronous rectification control circuitry is provided to reduce power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, and crossover-current protection. Special power-up sequencing is not required. The A3958 is supplied in a choice of two power packages, a 24-pin plastic DIP with exposed thermal tabs package suffix ‘B’ , and a 24-pin SOIC with internally fused pins package suffix ‘LB’ . In both cases, the power pins are at ground potential and need no electrical isolation. Each package type is lead Pb free, with 100% matte tin leadframe. LOGIC SUPPLY CP1 CP2 CP Functional Block Diagram LOAD SUPPLY CHARGE PUMP BANDGAP VDD CREG TSD UNDERVOLTAGE & FAULT DETECT CHARGE PUMP BANDGAP REGULATOR VREG PHASE ENABLE SYNC RECT MODE SYNC RECT DISABLE PWM MODE INT PWM MODE EXT GATE DRIVE MODE PHASE ENABLE CONTROL LOGIC FIXED OFF PROGRAMMABLE BLANK PWM TIMER DECAY CLOCK DATA STROBE RANGE SERIAL PORT 29319.31F SLEEP MODE ZERO CURRENT DETECT CURRENT SENSE RANGE REFERENCE BUFFER & DIVIDER OUTA OUTB SENSE CS RS

PDF Datasheet Preview

A3958 DMOS Full-Bridge PWM Motor Driver
±2 A, 50 V continuous output rating Low rDS on outputs 270 mΩ, typical Programmable mixed, fast, and slow current-decay modes Serial interface controls chip functions Synchronous rectification for low power dissipation Internal UVLO and thermal-shutdown circuitry Crossover-current protection

Packages:

Package B, 24-pin DIP with exposed tabs

Not to scale

Package LB, 24-pin SOIC with internally fused pins

Designed for pulse width modulated PWM current control of DC motors, the A3958 is capable of continuous output currents to ±2 A and operating voltages to 50 V. Internal fixed off-time PWM current-control timing circuitry can be programmed via a serial interface to operate in slow, fast, and mixed currentdecay modes.

PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a DC motor with externally applied PWM-control signals. The ENABLE input can be programmed via the serial port to PWM the bridge in fast or slow current decay. Internal synchronous rectification control circuitry is provided to reduce power dissipation during PWM operation.

Internal circuit protection includes thermal shutdown with hysteresis, and crossover-current protection. Special power-up sequencing is not required.

The A3958 is supplied in a choice of two power packages, a 24-pin plastic DIP with exposed thermal tabs package suffix ‘B’ , and a 24-pin SOIC with internally fused pins package suffix ‘LB’ . In both cases, the power pins are at ground potential and need no electrical isolation. Each package type is lead Pb free, with 100% matte tin leadframe.

LOGIC SUPPLY

CP1 CP2 CP

Functional Block Diagram

LOAD SUPPLY

CHARGE PUMP BANDGAP VDD CREG TSD

UNDERVOLTAGE & FAULT DETECT

CHARGE PUMP

BANDGAP REGULATOR

VREG

PHASE ENABLE SYNC RECT MODE SYNC RECT DISABLE PWM MODE INT PWM MODE EXT

GATE DRIVE

MODE PHASE ENABLE

CONTROL LOGIC

FIXED OFF

PROGRAMMABLE BLANK

PWM TIMER

DECAY

CLOCK DATA

STROBE

RANGE

SERIAL PORT
29319.31F

SLEEP MODE

ZERO CURRENT

DETECT

CURRENT SENSE

RANGE

REFERENCE BUFFER & DIVIDER

OUTA

OUTB SENSE

CS RS

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Datasheet ID: A3958SLBTR-T 516028