MB39A130A
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MB39A130APFT-G-BNDE1 (pdf) |
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MB39A130A MB39A130A 1ch DC/DC Buck Converter IC with Synchronous Rectification MB39A130A is a 1ch DC/DC Buck converter equipped with a bottom detection comparator and N-ch/N-ch synchronous rectification. It supports low on-duty operation to allow stable output of low voltages when there is a large difference between input and output voltages. MB39A130A realizes ultra-rapid response and high efficiency with built-in enhanced protection features. • Power conversion efficiency • Adjustable frequency setting by an external resistor :96 % Max. :100 kHz to 600 kHz • High accuracy reference voltage • Output voltage setting range V to 5 V or fixed to V/2.5 V • Adjustable output voltages setting by the external control • Input voltage range VIN V to 25 V • Inductor saturation detection function which can be set optional • Built-in over voltage protection function • Built-in under voltage protection function • Built-in over current protection function • Built-in Power-Good detection function • Built-in over temperature protection function • Built-in soft-start circuit without load dependence • Built-in discharge control circuit • Built-in synchronous rectification type output driver for N-ch MOS FET • Standby current 0 [µA] Typ. • Small package TSSOP-24 x [mm] • Digital TV • Photocopiers • STB • BD, DVD players/recorders • Projectors Various other advanced devices • San Jose, CA 95134-1709 • 408-943-2600 MB39A130A Contents Description 1 Features 1 Applications 1 Pin Assignment 3 Pin Descriptions 4 Block Diagram 5 Absolute Maximum Ratings 6 Recommended Operating Conditions 7 Electrical Characteristics 8 Diagram of Feedback Voltage Measurement Circuit 12 Typical Characteristics 13 Function 17 Reference Voltage Block REF 18 Under Voltage Lockout Protection Circuit Block UVLO 18 Soft-start Block Soft-Start 18 Discharge Block Discharge 18 ON/OFF Time Generator Block tON Generator 19 Output Voltage Setting Block VO REFIN Control, Error Comp. 20 Current Detection Block Current Sense 21 Over Current Detection Block ILIM Comp. 21 Inductor Saturation Detection Block LSAT Comp. 22 Over-voltage Protection Circuit Block OVP Comp. 23 Under-voltage Protection Circuit Block UVP Comp. 24 Power-Good Detection Circuit Block PGOOD Comp. 24 Output Block Drv-1, Drv-2 25 Control Block CTL 25 Bias Voltage Block VB Reg. 25 Over temperature Protection Circuit Block OTP 25 Protection Function Table 26 I/O Pin Equivalent Circuit Diagram 27 Example Application Circuit 30 Parts List 31 Application Note 32 Reference Data 53 Usage Precaution 57 Ordering Information 57 RoHS Compliance Information 57 Package Dimensions 58 Sales, Solutions, and Legal Information 60 Page 2 of 60 Pin Assignment GND 1 REFIN 2 VREF 3 CS 4 COVP 5 CUVP 6 PGOOD 7 CTL 8 LSAT 9 ILIM 10 +INC 11 −INC 12 TOP VIEW TSSOP-24 STD024 MB39A130A 24 FB 23 VO 22 RT 21 CB 20 OUT-1 19 LX 18 VBIN 17 VCC 16 VB 15 OUT-2 14 PGND 13 FSW Page 3 of 60 MB39A130A Pin Descriptions Pin No. Pin Name REFIN VREF COVP CUVP PGOOD LSAT ILIM +INC -INC PGND OUT-2 VBIN OUT-1 Ground pin. Reference voltage input pin for Error Comp. Reference voltage output pin. Soft-start time setting capacitor connection pin. Detection time setting capacitor connection pin for OVP function. The OVP function can be disabled by a short circuit with GND pin. Detection time setting capacitor connection pin for UVP function. The UVP function can be disabled by a short circuit with GND pin. Power-Good detection circuit output pin. Open-drain output Power supply control pin. IC changes to standby state when CTL is set to “L” level. Inductor oversaturation detection level setting voltage input pin. Over current detection level setting voltage input pin. Current detection block Current Sense input pin. Current detection block Current Sense input pin. Preset value switching pin for operating frequency. Ground pin for output circuit. Output pin for external low-side FET gate drive. Bias output pin for output circuit. Power supply pin. Bias voltage external input pin for output circuit and control circuit. Inductor and external high-side FET source and external low-side FET drain connection pin. Output pin for external high-side FET gate drive. Connection pin for boot strap capacitor. It connects a capacitor between CB and LX pins. Connection pin for tON time setting resistor. Input pin for DC/DC output voltage. Feedback pin for DC/DC output voltage. Page 4 of 60 MB39A130A Block Diagram <Discharge > CTL uvp otp RT 22 <Soft-Start > VREF CTL, uvlo VO 23 FB 24 2 REFIN +INC 11 -INC Ordering Information MB39A130APFT Package 24-pin plastic TSSOP STD024 Remarks RoHS Compliance Information The LSI products of Cypress with “E1” are compliant with RoHS Directive, and has observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls PBB , and polybrominated diphenyl ethers PBDE A product whose part number has trailing characters “E1” is RoHS compliant. Page 57 of 60 Package Dimensions Package Code STD024 MB39A130A AREA TOP VIEW C A-B D BOTTOM VIEW DETAIL A SEATING PLANE C A-B D 8 SIDE VIEW GAUGE PLANE DETAIL A SECTION A-A' DIMENSION SYMBOL MIN. NOM. MAX. 1 27 6 / / ' , 0 1 6 , 2 1 6 5 , 1 0 , / / , 0 7 5 ' , 0 1 6 , 2 1 , 1 * 1 ' 7 2 / 5 1 & , 1 * 3 5 6 0 < 0 ' , 0 1 6 , 2 1 , 1 * ' , 1 & / 8 ' 0 2 / ' / 6 + ' , 0 1 6 , 2 1 , 1 * ' 2 6 1 2 7 , 1 & / 8 ' , 1 7 5 / ' / 6 + 2 5 3 5 2 7 5 8 6 , 2 1 , 1 7 5 / ' / 6 + 2 5 3 5 2 7 5 8 6 , 2 1 6 + / / 1 2 7 & ' P 3 5 6 , ' ' D Q G ' , 0 1 6 , 2 1 5 ' 7 5 0 , 1 ' ' 7 8 0 + 7 + 3 & * 7 2 3 0 < % 6 0 / / 5 7 + 1 7 + 3 & * % 2 7 2 0 ' , 0 1 6 , 2 1 , 1 * D Q 5 ' 7 5 0 , 1 7 + 2 8 7 5 0 2 6 7 5 0 2 7 + 3 / 6 7 , % 2 ' & / 8 6 , 9 2 0 2 / / 6 + 7 + % 5 % 8 5 6 * 7 % 8 5 6 1 ' , 1 7 5 / ' / 6 + % 8 7 , 1 & / 8 ' , 1 * 1 0 , 6 0 7 & % 7 + 7 2 1 % 2 7 2 0 2 7 + 3 / 6 7 , % 2 ' < ' 7 8 0 6 % 7 2 % ' 7 5 0 , 1 ' 7 ' 7 8 0 + 1 , 6 7 + 0 , 0 8 0 1 8 0 % 5 2 7 5 0 , 1 / 3 2 6 , 7 , 2 1 6 2 5 7 + 6 3 & , , ' 3 & * / 1 * 7 + 7 + ' , 0 1 6 , 2 1 3 / < 7 2 7 + / 7 6 & 7 , 2 1 2 7 + / ' % 7 1 P 7 2 P 5 2 0 7 + / 7 , 3 ' , 0 1 6 , 2 1 E ' 2 6 1 2 7 , 1 & / 8 ' 7 + ' 0 % 5 3 5 2 7 5 8 6 , 2 1 / / 2 % / ' 0 % 5 3 5 2 7 5 8 6 , 2 1 6 + / / % P 7 2 7 / , 1 & 6 2 7 + E ' , 0 1 6 , 2 1 0 , 0 8 0 7 5 , & 2 1 ' , 7 , 2 1 7 + ' 0 % 0 1 2 % / 2 & 7 2 7 + / 2 5 ' , 8 2 7 + 2 7 7 + , 6 & + 0 5 7 8 5 , 6 2 3 7 , 2 1 / / , 7 , 6 1 2 7 3 5 6 1 7 + 1 3 , 1 , ' 1 7 , , 0 8 6 % / 2 & 7 , 7 + , 7 + , 1 ' 5 , 1 ' , & 7 ' , 6 ' , 1 ' 6 7 + 9 5 7 , & / ' , 6 7 1 & 5 2 0 7 + 6 7 , 1 * 3 / 1 7 2 7 + / 2 6 3 2 , 1 2 7 + 3 & * % 2 ' & / 8 ' , 1 * 7 + / , 1 2 5 7 + 5 0 1 + 1 & 0 1 2 & 9 , 7 ' 2 3 & * & 2 1 , * 8 5 7 , 2 1 6 JEDEC SPECIFICATION NO. REF N/A Page 58 of 60 MB39A130A Document History Document Title MB39A130A 1ch DC/DC Buck Converter IC with Synchronous Rectification Document Number 002-08423 Updated Ordering Information: Change the package name from FPT-24P-M09 to STD024 5641433 HIXT 02/24/2017 Deleted “EV Board Ordering Information” Deleted “Marking Format Lead Free Version ” Deleted “Labeling Sample Lead Free Version ” Deleted “MB39A130APFT Recommended Conditions of Moisture Sensitivity Level” Updated Package Dimensions Updated to Cypress format 5772193 MASG 06/13/2017 Adapted Cypress new logo. Page 59 of 60 MB39A130A Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Solutions Microcontrollers cypress.com/arm PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Automotive Clocks & Buffers Interface cypress.com/automotive cypress.com/clocks cypress.com/interface Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Internet of Things Memory Microcontrollers cypress.com/iot cypress.com/memory cypress.com/mcu Technical Support cypress.com/support PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless/RF cypress.com/wireless Cypress Semiconductor Corporation, This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC “Cypress” . This document, including any software or firmware included or referenced in this document “Software” , is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license without the right to sublicense 1 under its copyright rights in the Software a for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and b to distribute the Software in binary code form externally to end users either directly or indirectly through resellers and distributors , solely for use on Cypress hardware product units, and 2 under those claims of Cypress’s patents that are infringed by the Software as provided by Cypress, unmodified to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems including resuscitation equipment and surgical implants , pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage “Unintended Uses” . A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Page 60 of 60 |
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