TMC22153AKHC

TMC22153AKHC Datasheet

TMC22x5yA

Part	Datasheet
TMC22153AKHC	TMC22153AKHC (pdf)

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TMC22x5yA Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit • Very high performance, low cost • Adaptive comb-based decoding • Multiple pin-compatible versions - 3-line, 2-line, and band-split - 8- and 10-bit processing • Internal digital linestores • Supports NTSC/PAL and NTSC frame based decoding • Multiple input formats - CCIR-601/624 D1 , D2, CVBS, YC • Multiple output formats - CCIR-601/624 D1 , RGB, YCBCR • 10-18 Mpps data rate • Parallel and serial control interface • Single +5V power supply • Studio television equipment • Personal computer video input • MPEG and JPEG compression inputs Block Diagram BUFFER MASTER1-0 The TMC22x5yA family of Digital Video Decoders offers unprecedented, broadcast-quality video processing performance in a single chip. It accepts line-locked or subcarrierlocked composite, YC, or D1 digital video and produces digital components in a variety of formats. An internal three-line adaptive comb decoder structure produces optimal picture quality with a wide range of source material. NTSC/PAL and NTSC frame based decoding is supported with external memory. Full comb programmability allows the user to tailor the decoder’s response to a particular systems goals. A family of products offers 3-line, 2-line, and simple decoders in 8-bit and 10-bit in a pin and softwarecompatible format. Serial and parallel control ports are provided. These submicron CMOS devices are packaged in a 100-lead Metric Quad Flat Pack MQFP . Related Products • TMC22071 Genlocking Video Digitizer • TMC22x9x 8 bit Digital Video Encoders • TMC2081 Digital Video Mixer • TMC3003 Triple 10-bit D/A Converter • TMC1185 10 bit A/D converter • TMC2192 10 bit video encoder • TMC2072 Enhanced Genlocking Video Digitizer VIDEOA9-0 VIDEOB9-0 CLOCK LDV HSYNC VSYNC Input Processor Internal Sync Pulse Generator Linestore1 Linestore2 Y/C Split0 Y/C Split1 Adaptive Comb Filter Y/C Split2 Chroma Demod Comb Fail Burst Locked Loop Output Processor Parallel Control Global Control Serial Control G/Y9-0 B/Cb9-0 R/Cr9-0 FID2-0 DREF DHSYNC DVSYNC A1-0 R/W CS D 7-0 SET RESET SER SA2-0 SDA SCL 65-22x5y-01 TMC22x5yA PRODUCT SPECIFICATION Table of Contents Features Applications Description Block Diagram Contents List of Tables and Figures General Description Input Adaptive Comb Output Processor Parallel and Serial Microprocessor Interfaces................5 Pin Assignments Pin Control Register Control Register Definitions Decoder YC Separation Comb Filter Architecture for YC Separation YC Line-Based Comb D1 Line-Based Comb Filters NTSC Frame and Field Based Decoders Composite Frame-Based Comb Filters Composite Field-Based Comb Filters PAL Field Comb Decoders Composite PAL Field Comb Filters.............................42 The TMC22x5yA Comb Filter Architecture TMC22x5yA Functional Description.......................44 Input Bandsplit Filter BSF Comb Filter Adaptive Comb Fail Detection Generation of the Comb Fail Signals Luma Error Signals Hue and Saturation Error Picture Correlation Adapting the Comb Filter XLUT Digital Burst Locked Loop Color Kill Counter PAL Color Frame Bit Hue System Monitoring of the Burst Loop Error Clamp Circuit 55 Pedestal Removal 55 Clamp Generator 55 Luma Notch Filter 56 Matrix 56 Programmable U 56 Programmable V 56 Programmable Y 56 Programmable MS 56 Fixed B-Y and R-Y Scalars 56 Y Offset 57 Matrix 57 Examples of Output Matrix Operation 57 Simple Luma Color Correction 58 CBCR MSB Inversion 58 Output Rounding 58 Output 58 Decimating CBCR 58 Multiplexed YCBCR Output TRS Words Inserted ... 58 YC 58 The LDV Clock 58 Sync Pulse Generator 59 Internal Field and Line Numbering Scheme 59 Timing Parameters 61 Subcarrier Programming 61 Horizontal Timing 61 Horizontal and Vertical Timing Parameters................ 61 Vertical Blanking 62 VINDO Operation 65 Video 65 Pixel 65 Composite Line Grab 67 Parallel Microprocessor Interface 67 Serial Control Port 68 Equivalent Circuits and Threshold Levels 71 Absolute Maximum 72 Operating Conditions 73 Electrical 75 Switching 76 System Performance Characteristics 76 Programming 77 Programming Worksheet 81 Related Products 82 Ordering Information 84 PRODUCT SPECIFICATION TMC22x5yA List of Tables and Figures Table Table Table Table Table TMC22x5yA Decoder Family 4 Normalized Subcarrier Frequency as a Function of Pixel Data Rates....... 45 Comb Filter Architecture 48 Simple Example of an Adaptive Comb Filter Architecture 48 Adaption Modes 51 XLUT Input Selection 52 XLUT Output Function 52 XLUT Special Function Definitions..... 52 PAL-B,G,H,I Bruch Blanking Sequence 53 PAL-M Bruch Blanking Sequence 54 Blanking Level Selection 55 Adaptive Notch Threshold Control..... 55 Matrix 57 Output Format 58 NTSC Field and Line Numbering 59 PAL B,G,H,I Field and Line Numbering 59 PAL M Field and Line Numbering 59 Vertical Blanking Period 60 Vertical Burst Blanking Period............ 60 Table of Line Idents, LID[4:0] 60 Timing Offsets 61 PAL VINDO operation 63 Pixel Grab Control................................ 66 Parallel Port Control............................. 67 Serial Port Addresses 69 Figure Logic 4 Figure Pixel Data Format 4 Figure Fundamental Decoder Block Diagram 40 Figure Comparison of the Frequency Spectrum of NTSC and PAL Composite Video Signals 40 Figure Examples of Notch and Bandpass 41 Figure 41 Figure Chrominance Vector Rotation in PAL and NTSC 42 Figure Chrominance Vector Rotation Over 4 Fields in NTSC 42 Figure Chrominance Vector Rotation Over 4 Fields in 42 Figure TMC22x5yA Line Based Comb Filter Architecture 43 Figure Input Processor 44 Figure Complementary Bandsplit Filter 44 Figure Bandsplit Filter, Full Frequency Response 45 Figure Bandsplit Filter, Passband Response 45 Figure Block Diagram of Comb Filter Input 46 Figure Signal Flow Around the Adaptive Comb Filter 47 Figure Example of a Comb Fail Using a NTSC Two Line Comb Filter........................... 49 Figure Generation of Upper and Lower Comb Fail Signals 50 Figure Comb Filter Selection 51 Figure XLUT Input Selection 52 Figure Block Diagram of Digital Burst Locked Loop 53 Figure Gaussian Low Pass Filters.................. 54 Figure Gaussian LPF Passband Detail........... 54 Figure Output Processor Block Diagram....... 55 Figure Adaptive Notch Filters 56 Figure Luminance Notch Filter 56 Figure Horizontal Timing 61 Figure External HSYNC and VSYNC Timing for Field 1 3, 5, or 7 62 Figure NTSC Vertical Interval.......................... 62 Figure PAL-B,G,H,I,N Vertical Interval............ 62 Figure PAL-M Vertical Interval 63 Figure Pixel Grab Locations............................ 64 Figure Relationship Between Pixel Count and Pixel Grab Value............................ 65 Figure Microprocessor Parallel Port Write 66 Figure Microprocessor Parallel Port Read 68 Figure Serial Port Read/Write Timing............. 69 Figure Serial Interface Typical Byte Transfer........................... 70 Figure Equivalent Digital Input Circuit 71 Figure Equivalent Digital Output 71 Figure Threshold Levels for Three-state........ 71 Figure Input Timing Parameters 72 Figure Functional Block Diagram of the TMC22x5yA G/Y, B/U, and R/V Output 73 Figure Output Timing Parameters 74 TMC22x5yA PRODUCT SPECIFICATION The TMC22x5yA digital decoder can be used as a universal input to digital video processing systems by decoding digital composite video and transcoding digital component inputs into a common data format. The digital comb decoder implements one of sixteen comb architectures to produce luminance and color difference component signals which are virtually free of the cross-color and cross-luminance artifacts associated with simple bandsplit decoders. Table TMC22x5yA Decoder Family TMC2215yA TMC2205yA Function 321321 10-bit Data 8-bit Data D1 Interface Line-Locked Mode fSC-Locked Mode Genlock Mode NTSC Frame Comb NTSC/PAL Field Comb Ordering Information Product Number TMC22051AKHC TMC22052AKHC TMC22053AKHC TMC22151AKHC TMC22152AKHC TMC22153AKHC Temperature Range 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C PRODUCT SPECIFICATION Decoding Simple 2-Line Comb 3-Line Comb Simple 2-Line Comb 3-Line Comb Resolution 8 bit 8 bit 8 bit 10 bit 10 bit 10 bit Package 100-Lead MQFP 100-Lead MQFP 100-Lead MQFP 100-Lead MQFP 100-Lead MQFP 100-Lead MQFP Package Marking 22051AKHC 22052AKHC 22053AKHC 22151AKHC 22152AKHC 22153AKHC DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: Life support devices or systems are devices or systems which, a are intended for surgical implant into the body, or b support or sustain life, and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 2/4/03 0.0m 001 Stock#DS7022x5yA 2003 Fairchild Semiconductor Corporation

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TMC22x5yA

Multistandard Digital Video Decoder

Three-Line Adaptive Comb Decoder Family, 8 & 10 bit
• Very high performance, low cost
• Adaptive comb-based decoding
• Multiple pin-compatible versions
- 3-line, 2-line, and band-split - 8- and 10-bit processing
• Internal digital linestores
• Supports NTSC/PAL and NTSC frame based decoding
• Multiple input formats - CCIR-601/624 D1 , D2, CVBS, YC
• Multiple output formats - CCIR-601/624 D1 , RGB, YCBCR
• 10-18 Mpps data rate
• Parallel and serial control interface
• Single +5V power supply
• Studio television equipment
• Personal computer video input
• MPEG and JPEG compression inputs

Block Diagram

BUFFER MASTER1-0

The TMC22x5yA family of Digital Video Decoders offers unprecedented, broadcast-quality video processing performance in a single chip. It accepts line-locked or subcarrierlocked composite, YC, or D1 digital video and produces digital components in a variety of formats.

An internal three-line adaptive comb decoder structure produces optimal picture quality with a wide range of source material. NTSC/PAL and NTSC frame based decoding is supported with external memory. Full comb programmability allows the user to tailor the decoder’s response to a particular systems goals.

A family of products offers 3-line, 2-line, and simple decoders in 8-bit and 10-bit in a pin and softwarecompatible format. Serial and parallel control ports are provided. These submicron CMOS devices are packaged in a 100-lead Metric Quad Flat Pack MQFP .

Related Products
• TMC22071 Genlocking Video Digitizer
• TMC22x9x 8 bit Digital Video Encoders
• TMC2081 Digital Video Mixer
• TMC3003 Triple 10-bit D/A Converter
• TMC1185 10 bit A/D converter
• TMC2192 10 bit video encoder
• TMC2072 Enhanced Genlocking Video Digitizer

VIDEOA9-0

VIDEOB9-0

CLOCK LDV

HSYNC VSYNC

Input Processor

Internal Sync Pulse Generator

Linestore1 Linestore2

Y/C Split0 Y/C Split1

Adaptive Comb Filter

Y/C Split2

Chroma Demod

Comb Fail

Burst Locked Loop

Output Processor

Parallel Control

Global Control

Serial Control

G/Y9-0 B/Cb9-0 R/Cr9-0

FID2-0 DREF DHSYNC DVSYNC

A1-0 R/W CS D 7-0 SET RESET SER SA2-0 SDA SCL
65-22x5y-01

TMC22x5yA

PRODUCT SPECIFICATION

Table of Contents

Features Applications Description Block Diagram Contents List of Tables and Figures General Description

Input Adaptive Comb Output Processor Parallel and Serial Microprocessor Interfaces................5 Pin Assignments Pin Control Register Control Register Definitions Decoder YC Separation Comb Filter Architecture for YC Separation YC Line-Based Comb D1 Line-Based Comb Filters NTSC Frame and Field Based Decoders Composite Frame-Based Comb Filters Composite Field-Based Comb Filters PAL Field Comb Decoders Composite PAL Field Comb Filters.............................42 The TMC22x5yA Comb Filter Architecture TMC22x5yA Functional Description.......................44 Input Bandsplit Filter BSF Comb Filter Adaptive Comb Fail Detection Generation of the Comb Fail Signals Luma Error Signals Hue and Saturation Error Picture Correlation Adapting the Comb Filter XLUT Digital Burst Locked Loop Color Kill Counter PAL Color Frame Bit Hue System Monitoring of the Burst Loop Error
Clamp Circuit 55 Pedestal Removal 55 Clamp Generator 55 Luma Notch Filter 56 Matrix 56 Programmable U 56 Programmable V 56 Programmable Y 56 Programmable MS 56 Fixed B-Y and R-Y Scalars 56 Y Offset 57 Matrix 57 Examples of Output Matrix Operation 57 Simple Luma Color Correction 58 CBCR MSB Inversion 58 Output Rounding 58 Output 58 Decimating CBCR 58 Multiplexed YCBCR Output TRS Words Inserted ... 58 YC 58 The LDV Clock 58 Sync Pulse Generator 59 Internal Field and Line Numbering Scheme 59 Timing Parameters 61 Subcarrier Programming 61 Horizontal Timing 61 Horizontal and Vertical Timing Parameters................ 61 Vertical Blanking 62 VINDO Operation 65 Video 65 Pixel 65 Composite Line Grab 67 Parallel Microprocessor Interface 67 Serial Control Port 68 Equivalent Circuits and Threshold Levels 71 Absolute Maximum 72 Operating Conditions 73 Electrical 75 Switching 76 System Performance Characteristics 76 Programming 77 Programming Worksheet 81 Related Products 82 Ordering Information 84

PRODUCT SPECIFICATION

TMC22x5yA

List of Tables and Figures

Table

Table

Table

Table

Table

TMC22x5yA Decoder Family 4 Normalized Subcarrier Frequency as a Function of Pixel Data Rates....... 45 Comb Filter Architecture 48 Simple Example of an Adaptive Comb Filter Architecture 48 Adaption Modes 51 XLUT Input Selection 52 XLUT Output Function 52 XLUT Special Function Definitions..... 52 PAL-B,G,H,I Bruch Blanking Sequence 53 PAL-M Bruch Blanking Sequence 54 Blanking Level Selection 55 Adaptive Notch Threshold Control..... 55 Matrix 57 Output Format 58 NTSC Field and Line Numbering 59 PAL B,G,H,I Field and Line Numbering 59 PAL M Field and Line Numbering 59 Vertical Blanking Period 60 Vertical Burst Blanking Period............ 60 Table of Line Idents, LID[4:0] 60 Timing Offsets 61 PAL VINDO operation 63 Pixel Grab Control................................ 66 Parallel Port Control............................. 67 Serial Port Addresses 69

Figure Logic 4 Figure Pixel Data Format 4 Figure Fundamental Decoder

Block Diagram 40 Figure Comparison of the Frequency

Spectrum of NTSC and PAL Composite Video Signals 40 Figure Examples of Notch and Bandpass 41 Figure 41 Figure Chrominance Vector Rotation in PAL and NTSC 42 Figure Chrominance Vector Rotation Over 4 Fields in NTSC 42 Figure Chrominance Vector Rotation Over 4 Fields in 42 Figure TMC22x5yA Line Based Comb Filter Architecture 43

Figure Input Processor 44 Figure Complementary Bandsplit Filter 44 Figure Bandsplit Filter, Full Frequency

Response 45 Figure Bandsplit Filter, Passband

Response 45 Figure Block Diagram of Comb Filter Input 46 Figure Signal Flow Around the Adaptive

Comb Filter 47 Figure Example of a Comb Fail Using a NTSC

Two Line Comb Filter........................... 49 Figure Generation of Upper and Lower Comb

Fail Signals 50 Figure Comb Filter Selection 51 Figure XLUT Input Selection 52 Figure Block Diagram of Digital Burst

Locked Loop 53 Figure Gaussian Low Pass Filters.................. 54 Figure Gaussian LPF Passband Detail........... 54 Figure Output Processor Block Diagram....... 55 Figure Adaptive Notch Filters 56 Figure Luminance Notch Filter 56 Figure Horizontal Timing 61 Figure External HSYNC and VSYNC Timing
for Field 1 3, 5, or 7 62 Figure NTSC Vertical Interval.......................... 62 Figure PAL-B,G,H,I,N Vertical Interval............ 62 Figure PAL-M Vertical Interval 63 Figure Pixel Grab Locations............................ 64 Figure Relationship Between Pixel Count
and Pixel Grab Value............................ 65 Figure Microprocessor Parallel Port

Write 66 Figure Microprocessor Parallel Port

Read 68 Figure Serial Port Read/Write Timing............. 69 Figure Serial Interface

Typical Byte Transfer........................... 70 Figure Equivalent Digital Input Circuit 71 Figure Equivalent Digital Output 71 Figure Threshold Levels for Three-state........ 71 Figure Input Timing Parameters 72 Figure Functional Block Diagram of the

TMC22x5yA G/Y, B/U, and R/V Output 73 Figure Output Timing Parameters 74

TMC22x5yA

PRODUCT SPECIFICATION

The TMC22x5yA digital decoder can be used as a universal input to digital video processing systems by decoding digital composite video and transcoding digital component inputs into a common data format.

The digital comb decoder implements one of sixteen comb architectures to produce luminance and color difference component signals which are virtually free of the cross-color and cross-luminance artifacts associated with simple bandsplit decoders.

Table TMC22x5yA Decoder Family

TMC2215yA TMC2205yA

Function
321321
10-bit Data
8-bit Data

D1 Interface

Line-Locked Mode
fSC-Locked Mode Genlock Mode

NTSC Frame Comb

NTSC/PAL Field Comb
Ordering Information

Product Number TMC22051AKHC TMC22052AKHC TMC22053AKHC TMC22151AKHC TMC22152AKHC TMC22153AKHC

Temperature Range
0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C

PRODUCT SPECIFICATION

Decoding Simple
2-Line Comb 3-Line Comb

Simple 2-Line Comb 3-Line Comb

Resolution 8 bit 8 bit 8 bit 10 bit 10 bit 10 bit

Package 100-Lead MQFP 100-Lead MQFP 100-Lead MQFP 100-Lead MQFP 100-Lead MQFP 100-Lead MQFP

Package Marking 22051AKHC 22052AKHC 22053AKHC 22151AKHC 22152AKHC 22153AKHC

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

Life support devices or systems are devices or systems which, a are intended for surgical implant into the body, or b support or sustain life, and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
2/4/03 0.0m 001 Stock#DS7022x5yA 2003 Fairchild Semiconductor Corporation

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Datasheet ID: TMC22153AKHC 634796