SCANPSC100FSC

SCANPSC100FSC Datasheet

SCANPSC100F Embedded Boundary Scan Controller IEEE Support

Part	Datasheet
SCANPSC100FSC	SCANPSC100FSC (pdf)

Related Parts	Information
SCANPSC100FSCX	SCANPSC100FSCX

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SCANPSC100F Embedded Boundary Scan Controller IEEE Support SCANPSC100F Embedded Boundary Scan Controller IEEE Support The SCANPSC100F is designed to interface a generic parallel processor bus to a serial scan test bus. It is useful in improving scan throughput when applying serial vectors to system test circuitry and reduces the software overhead that is associated with applying serial patterns with a parallel processor. The SCANPSC100F operates by serializing data from the parallel bus for shifting through the chain of compliant components i.e., scan chain . Scan data returning from the scan chain is placed on the parallel port to be read by the host processor. Up to two scan chains can be directly controlled with the SCANPSC100F via two independent TMS pins. Scan control is supplied with user specific patterns which makes the SCANPSC100F protocol-independent. Overflow and underflow conditions are prevented by stopping the test clock. A 32-bit counter is used to program the number of TCK cycles required to complete a scan operation within the boundary scan chain or to complete a SCANPSC100F Built-In Self Test BIST operation. SCANPSC100F device drivers and embedded test application code are available with Fairchild’s SCAN Ease software tools. s Compatible with IEEE Std. JTAG Test Access Port and Boundary Scan Architecture s Supported by Fairchild’s SCAN Ease Embedded Application Software Enabler Software s Uses generic, asynchronous processor interface compatible with a wide range of processors and PCLK frequencies s Directly supports up to two scan chains s 16-bit Serial Signature Compaction SSC at the Test Data In TDI port s Automatically produces pseudo-random patterns at the Test Data Out TDO port s Fabricated on µm CMOS process s Supports test clock TCK frequencies up to 25 MHz s TTL-compatible inputs full-swing CMOS outputs with 24 mA source/sink capability Ordering Code: Order Number Package Number Package Description SCANPSC100FSC M28B 28-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram is a trademark of Fairchild Semiconductor Corporation. 2000 Fairchild Semiconductor Corporation DS010968 SCANPSC100F Pin Descriptions Pin Name RST Input SCK Input The Reset pin is an asynchronous input that, when LOW, initializes the SCANPSC100. Mode bits, Shifter/Buffer and CNT32 control logic, TCK Control, and the PPI are all initialized to defined states. RST has hysteresis for improved noise immunity. The System Clock drives all internal timing. The test clock, TCK, is a gated and buffered version of SCK. SCK has hysteresis for improved immunity. OE Input Output Enable 3-STATEs all SSI outputs when HIGH. A 20 pull-up resistor is connected to automatically 3-STATE these outputs when this signal is floating. CE Input Chip Enable, when LOW, enables the PPI for byte transfers. D 7:0 and RDY are 3-STATEd if CE is HIGH. CE has hysteresis for improved noise immunity. R/W Input STB Input A 2:0 Input D 7:0 I/O INT Output Read/Write defines a PPI when HIGH, Write when LOW. R/W has hysteresis for improved noise immunity. Strobe is used for timing all PPI byte transfers. D 7:0 are 3-STATEd when STB is HIGH. All other PPI inputs must meet specified setup and hold times with respect to this signal. STB has hysteresis for noise improved immunity. The Address pins are used to select the register to be written to or read from. Bidirectional pins used to transfer parallel data to and from the SCANPSC100. Interrupt is used to trigger a host interrupt for any of the defined interrupt events. INT is active HIGH. Ready is used to synchronize asynchronous byte transfers between the host and the SCANPSC100. 3-STATE Output When LOW, RDY signals that the addressed register is ready to be accessed RDY is enabled when CE is LOW Test Data Out is the serial scan output from the SCANPSC100. TDO is enabled when OE is LOW. 3-STATE Output TMS 1:0 The Test Mode Select pins are serial outputs used to supply control logic to the UUT. 3-STATE Output TMS 1:0 are enabled when OE is LOW. The Test Clock output is a buffered version of SCK for distribution in the UUT. 3-STATE Output TCK Control logic starts and stops TCK to prevent overflow and underflow conditions. TCK is enabled when OE is LOW. TDI Input Test Data In is the serial scan input to the SCANPSC100. A 20 pull-up resistor is connected to force TDI to a logic 1 when the TDO line from the UUT is floating. FRZ Input The Freeze pin is used to asynchronously generate a user-specific pulse on TCK. If the FRZ Enable Mode bit is set, TCK will be forced HIGH if FRZ goes HIGH. FRZ has hysteresis for improved noise immunity. SCANPSC100F Chip Architecture The SCANPSC100 is designed to act together with a parallel bus host as a serial test bus master. Parallel data is written by the host to the SCANPSC100, which serializes the data for application to a serial test bus. Serial data returning from the target scan chain s is placed on the processor port for parallel reads. Several features are included in the SCANPSC100 which make scan test communication more convenient and efficient. Figure 1 shows the major functional blocks of the SCANPSC100 design. The Parallel Processor Interface PPI is an asynchronous, 8-bit parallel interface which is used by the host processor to write and read data. The PPI generates the necessary internal data, address, and control signals to complete internal write and read operations. The Serial Scan Interface SSI consists of a bank of double-buffered parallel/serial shift registers i.e., a 2 x 8 bit FIFO , or Shifter/Buffers. The double buffering improves efficiency by allowing parallel writes or reads to/from one of the two 8-bit FIFOs within the shifter/buffer while the other FIFO is shifting data to/from the scan chain. Three Shifter/ Buffers are provided for outgoing serial data and one for incoming serial data. Test Data Out TDO is for scanning out test data while the two Test Mode Select signals TMS0/1 are used to provide user specific control data.

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SCANPSC100F Embedded Boundary Scan Controller IEEE Support

SCANPSC100F Embedded Boundary Scan Controller IEEE Support

The SCANPSC100F is designed to interface a generic parallel processor bus to a serial scan test bus. It is useful in improving scan throughput when applying serial vectors to system test circuitry and reduces the software overhead that is associated with applying serial patterns with a parallel processor. The SCANPSC100F operates by serializing data from the parallel bus for shifting through the chain of compliant components i.e., scan chain . Scan data returning from the scan chain is placed on the parallel port to be read by the host processor. Up to two scan chains can be directly controlled with the SCANPSC100F via two independent TMS pins. Scan control is supplied with user specific patterns which makes the SCANPSC100F protocol-independent. Overflow and underflow conditions are prevented by stopping the test clock. A 32-bit counter is used to program the number of TCK cycles required to complete a scan operation within the boundary scan chain or to complete a SCANPSC100F Built-In Self Test BIST operation. SCANPSC100F device drivers and embedded test application code are available with Fairchild’s SCAN Ease software tools.
s Compatible with IEEE Std. JTAG Test Access Port and Boundary Scan Architecture
s Supported by Fairchild’s SCAN Ease Embedded Application Software Enabler Software
s Uses generic, asynchronous processor interface compatible with a wide range of processors and PCLK frequencies
s Directly supports up to two scan chains s 16-bit Serial Signature Compaction SSC at the Test

Data In TDI port s Automatically produces pseudo-random patterns at the

Test Data Out TDO port s Fabricated on µm CMOS process s Supports test clock TCK frequencies up to
25 MHz s TTL-compatible inputs full-swing CMOS outputs with
24 mA source/sink capability
Ordering Code:

Order Number Package Number

Package Description

SCANPSC100FSC

M28B
28-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram
is a trademark of Fairchild Semiconductor Corporation.
2000 Fairchild Semiconductor Corporation DS010968

SCANPSC100F

Pin Descriptions

Pin Name

RST Input SCK Input

The Reset pin is an asynchronous input that, when LOW, initializes the SCANPSC100. Mode bits, Shifter/Buffer and CNT32 control logic, TCK Control, and the PPI are all initialized to defined states. RST has hysteresis for improved noise immunity.

The System Clock drives all internal timing. The test clock, TCK, is a gated and buffered version of SCK. SCK has hysteresis for improved immunity.

OE Input

Output Enable 3-STATEs all SSI outputs when HIGH. A 20 pull-up resistor is connected to automatically 3-STATE these outputs when this signal is floating.

CE Input

Chip Enable, when LOW, enables the PPI for byte transfers. D 7:0 and RDY are 3-STATEd if CE is HIGH. CE has hysteresis for improved noise immunity.

R/W Input STB Input

A 2:0 Input D 7:0 I/O INT Output

Read/Write defines a PPI when HIGH, Write when LOW. R/W has hysteresis for improved noise immunity.

Strobe is used for timing all PPI byte transfers. D 7:0 are 3-STATEd when STB is HIGH. All other PPI inputs must meet specified setup and hold times with respect to this signal. STB has hysteresis for noise improved immunity.

The Address pins are used to select the register to be written to or read from.

Bidirectional pins used to transfer parallel data to and from the SCANPSC100.

Interrupt is used to trigger a host interrupt for any of the defined interrupt events. INT is active HIGH.

Ready is used to synchronize asynchronous byte transfers between the host and the SCANPSC100.
3-STATE Output When LOW, RDY signals that the addressed register is ready to be accessed RDY is enabled when

CE is LOW

Test Data Out is the serial scan output from the SCANPSC100. TDO is enabled when OE is LOW.
3-STATE Output

TMS 1:0

The Test Mode Select pins are serial outputs used to supply control logic to the UUT.
3-STATE Output TMS 1:0 are enabled when OE is LOW.

The Test Clock output is a buffered version of SCK for distribution in the UUT.
3-STATE Output TCK Control logic starts and stops TCK to prevent overflow and underflow conditions.

TCK is enabled when OE is LOW.

TDI Input

Test Data In is the serial scan input to the SCANPSC100. A 20 pull-up resistor is connected to force TDI to a logic 1 when the TDO line from the UUT is floating.

FRZ Input

The Freeze pin is used to asynchronously generate a user-specific pulse on TCK. If the FRZ Enable Mode bit is set, TCK will be forced HIGH if FRZ goes HIGH. FRZ has hysteresis for improved noise immunity.

SCANPSC100F

Chip Architecture

The SCANPSC100 is designed to act together with a parallel bus host as a serial test bus master. Parallel data is written by the host to the SCANPSC100, which serializes the data for application to a serial test bus. Serial data returning from the target scan chain s is placed on the processor port for parallel reads. Several features are included in the SCANPSC100 which make scan test communication more convenient and efficient.

Figure 1 shows the major functional blocks of the SCANPSC100 design. The Parallel Processor Interface PPI is an asynchronous, 8-bit parallel interface which is used by the host processor to write and read data. The PPI generates the necessary internal data, address, and control signals to complete internal write and read operations.

The Serial Scan Interface SSI consists of a bank of double-buffered parallel/serial shift registers i.e., a 2 x 8 bit FIFO , or Shifter/Buffers. The double buffering improves efficiency by allowing parallel writes or reads to/from one of the two 8-bit FIFOs within the shifter/buffer while the other FIFO is shifting data to/from the scan chain. Three Shifter/ Buffers are provided for outgoing serial data and one for incoming serial data. Test Data Out TDO is for scanning out test data while the two Test Mode Select signals TMS0/1 are used to provide user specific control data.

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Datasheet ID: SCANPSC100FSC 634707