SCAN18540TSSC

SCAN18540TSSC Datasheet

SCAN18540T Inverting Line Driver with 3-STATE Outputs

Part	Datasheet
SCAN18540TSSC	SCAN18540TSSC (pdf)

Related Parts	Information
SCAN18540TSSCX	SCAN18540TSSCX

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SCAN18540T Inverting Line Driver with 3-STATE Outputs SCAN18540T Inverting Line Driver with 3-STATE Outputs The SCAN18540T is a high speed, low-power line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented paired output enable control signals. This device is compliant with IEEE Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input TDI , Test Data Out TDO , Test Mode Select TMS , and Test Clock TCK . s IEEE JTAG compliant s Dual output enable signals per byte s 3-STATE outputs for bus-oriented applications s 9-bit data busses for parity applications s Reduced-swing outputs source 32 mA/sink 64 mA s Guaranteed to drive transmission line to TTL input levels of 0.8V and 2.0V s TTL compatible inputs s 25 mil pitch SSOP Shrink Small Outline Package s Includes CLAMP and HIGHZ instructions s Member of Fairchild’s SCAN products Ordering Code: Order Number Package Number Package Description SCAN18540TSSC MS54A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide Connection Diagram Pin Descriptions Pin Names AOE1, AOE2 BOE1, BOE2 Description Input pins, A side Input pins, B side 3-STATE Output Enable Input pins, A side 3-STATE Output Enable Input pins, B side Output pins, A side Output pins, B side Truth Tables AOE1 L H X L Inputs AOE2 L X H L Inputs BOE1 BOE2 H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level Z = High Impedance 2000 Fairchild Semiconductor Corporation DS010964 SCAN18540T Block Diagrams Byte-A Tap Controller Byte-B Note BSR stands for Boundary Scan Register SCAN18540T Description of BOUNDARY-SCAN Circuitry The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Std The upper six bits are unique to the SCAN18540T device. SCAN CMOS Test Access Logic devices do not include the IEEE optional identification register. Therefore, this unique captured value can be used as a “pseudo ID” code to confirm that the correct device is placed in the appropriate location in the boundary scan chain. Instruction Register Scan Chain Definition Bypass Register Scan Chain Definition Logic 0 The INSTRUCTION register is an 8-bit register which captures the default value of The two least significant bits of this captured value 01 are required by IEEE Instruction Code Instruction EXTEST SAMPLE/PRELOAD CLAMP All Others HIGH-Z BYPASS

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SCAN18540T Inverting Line Driver with 3-STATE Outputs

SCAN18540T Inverting Line Driver with 3-STATE Outputs

The SCAN18540T is a high speed, low-power line driver featuring separate data inputs organized into dual 9-bit bytes with byte-oriented paired output enable control signals. This device is compliant with IEEE Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input TDI , Test Data Out TDO , Test Mode Select TMS , and Test Clock TCK .
s IEEE JTAG compliant s Dual output enable signals per byte s 3-STATE outputs for bus-oriented applications s 9-bit data busses for parity applications s Reduced-swing outputs source 32 mA/sink 64 mA s Guaranteed to drive transmission line to TTL input
levels of 0.8V and 2.0V s TTL compatible inputs s 25 mil pitch SSOP Shrink Small Outline Package s Includes CLAMP and HIGHZ instructions s Member of Fairchild’s SCAN products
Ordering Code:

Order Number Package Number

Package Description

SCAN18540TSSC

MS54A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide

Connection Diagram

Pin Descriptions

Pin Names

AOE1, AOE2 BOE1, BOE2

Description Input pins, A side Input pins, B side 3-STATE Output Enable Input pins, A side 3-STATE Output Enable Input pins, B side Output pins, A side Output pins, B side

Truth Tables

AOE1 L H X L

Inputs

AOE2 L X H L

Inputs

BOE1

BOE2

H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level Z = High Impedance
2000 Fairchild Semiconductor Corporation DS010964

SCAN18540T

Block Diagrams

Byte-A

Tap Controller

Byte-B

Note BSR stands for Boundary Scan Register

SCAN18540T

Description of BOUNDARY-SCAN Circuitry

The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data.

Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high.

The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low.

Std The upper six bits are unique to the SCAN18540T device. SCAN CMOS Test Access Logic devices do not include the IEEE optional identification register. Therefore, this unique captured value can be used as a “pseudo ID” code to confirm that the correct device is placed in the appropriate location in the boundary scan chain.

Instruction Register Scan Chain Definition

Bypass Register Scan Chain Definition Logic 0

The INSTRUCTION register is an 8-bit register which captures the default value of The two least significant bits of this captured value 01 are required by IEEE

Instruction Code

Instruction

EXTEST SAMPLE/PRELOAD

CLAMP

All Others

HIGH-Z BYPASS

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Datasheet ID: SCAN18540TSSC 634706