RMBA19500A

RMBA19500A Datasheet

RMBA19500A

Part	Datasheet
RMBA19500A	RMBA19500A (pdf)

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RMBA19500A May 2004 RMBA19500A PCS1900 2 Watt GaAs MMIC Power Amplifier The RMBA19500A is a highly linear Power Amplifier. The two stage circuit uses our pHEMT process. It has been designed for use as a driver stage for PCS1900 base stations, or as the output stage for Micro- and Pico-Cell base stations. The amplifier has been optimized for high linearity requirements for PCS operation. • 2 Watt linear output power at 36 dBc ACPR1 for CDMA operation • OIP3 43 dBm at 27 and 30 dBm output • Small Signal Gain of > 30 dB • Small outline SMD package Absolute Ratings Symbol Vd Vg PIN TC TSTG Parameter Drain Supply Voltage1 Gate Supply Voltage max absolute RF Input Power from source Operating Case Temperature Range Storage Temperature Range Ratings +10 -5 +5 -30 to +85 -40 to +100 Units V dBm °C °C Electrical Characteristics2 Parameter Frequency Range Gain Small Signal Over MHz Gain Variation Over Frequency Range Over Temperature Range Noise Figure P1dB Output Power CDMA3 PAE 33 dBm Pout OIP34 Drain Voltage Vdd Gate Voltage VG1, 2 and VG3 5 Quiescent currents Idq1, 2 and Idq3 5 Thermal Resistance Channel to Case RJC Min 1930 33 43 -2 24 45 180, 445 11 Max 1990 Units MHz dB dB dBm % dBm V mA °C/W Notes Only under quienscent RF applied. VDD = 7.0V, TC = 25°C. Part mounted on evaluation board with input and output matching to 9 Channel Forward Link QPSK Source Mbps modulation rate. CDMA ACPR1 is measured using the ratio of the average power within the MHz channel at band center to the average power within a 30 KHz bandwidth at an 885 KHz offset. Minimum CDMA output power is met with ACPR1 > 36 dBc. OIP3 specifications are achieved for power output levels of 27 and 30 dBm per tone with tone spacing of MHz at band-center with adjusted supply and bias conditions of Vdd = 6.5V and IdqTotal = 625mA see Note VG1,2 and VG3 must be individually adjusted to achieve IDQ1,2 and IDQ3. A single VGG bias supply adjusted to achieve IDQTOTAL = 625mA can be used with nearly equivalent performance. Values for IDQ1,2 and IDQ3 shown have been optimized for CDMA operation. IDQ1, 2 and IDQ3 or IDQTOTAL can be adjusted to optimize the linearity of the amplifier for other modulation systems. The device requires external input and output matching to as shown in Figure 3 and the Parts List. 2004 Fairchild Semiconductor Corporation RMBA19500A Application Information CAUTION THIS IS AN ESD SENSITIVE DEVICE The following describes a procedure for evaluating the RMBA19500A, a monolithic high efficiency power amplifier, in a surface mount package, designed for use as a driver stage for PCS1900 Base station or as the final output stage for Microand Pico-Cell base stations. Figure 1 shows the package outline and the pin designations. Figure 2 shows the functional block diagram of the packaged product. The RMBA19500A requires external passive components for DC bias and RF input and output matching circuits as shown in Figure 3 and the Parts List. A recommended schematic circuit is shown in Figure The gate biases for the three stages of the amplifier may be set by simple resistive voltage dividers. Figure 4 shows a typical layout of an evaluation board, corresponding to the schematic circuits of Figure The following designations should be noted: 1 Pin designations are as shown in Figure 2 Vg1, Vg2, and Vg3 are the Gate Voltages negative applied at the pins of the package. 3 Vgg1, 2, and Vgg3 are the negative supply voltages at the evaluation board terminals Vg1 and Vg2 are tied together . 4 Vd1, Vd2, and Vd3 are the Drain Voltages positive applied at the pins of the package. 5 Vdd is the positive supply voltage at the evaluation board terminal Vd1, Vd2, and Vd3 are tied together .

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RMBA19500A

May 2004

RMBA19500A

PCS1900 2 Watt GaAs MMIC Power Amplifier

The RMBA19500A is a highly linear Power Amplifier. The two stage circuit uses our pHEMT process. It has been designed for use as a driver stage for PCS1900 base stations, or as the output stage for Micro- and Pico-Cell base stations. The amplifier has been optimized for high linearity requirements for PCS operation.
• 2 Watt linear output power at 36 dBc ACPR1 for CDMA operation
• OIP3 43 dBm at 27 and 30 dBm output
• Small Signal Gain of > 30 dB
• Small outline SMD package

Absolute Ratings

Symbol Vd Vg PIN TC TSTG

Parameter Drain Supply Voltage1 Gate Supply Voltage max absolute RF Input Power from source Operating Case Temperature Range Storage Temperature Range

Ratings +10 -5 +5
-30 to +85 -40 to +100

Units V
dBm °C °C

Electrical Characteristics2

Parameter Frequency Range Gain Small Signal Over MHz Gain Variation

Over Frequency Range Over Temperature Range Noise Figure P1dB Output Power CDMA3 PAE 33 dBm Pout OIP34 Drain Voltage Vdd Gate Voltage VG1, 2 and VG3 5 Quiescent currents Idq1, 2 and Idq3 5 Thermal Resistance Channel to Case RJC

Min 1930
33 43 -2
24 45
180, 445 11

Max 1990

Units MHz dB
dB dBm % dBm V mA °C/W

Notes Only under quienscent RF applied. VDD = 7.0V, TC = 25°C. Part mounted on evaluation board with input and output matching to 9 Channel Forward Link QPSK Source Mbps modulation rate. CDMA ACPR1 is measured using the ratio of the average power within the MHz channel
at band center to the average power within a 30 KHz bandwidth at an 885 KHz offset. Minimum CDMA output power is met with ACPR1 > 36 dBc. OIP3 specifications are achieved for power output levels of 27 and 30 dBm per tone with tone spacing of MHz at band-center with adjusted supply and bias
conditions of Vdd = 6.5V and IdqTotal = 625mA see Note VG1,2 and VG3 must be individually adjusted to achieve IDQ1,2 and IDQ3. A single VGG bias supply adjusted to achieve IDQTOTAL = 625mA can be used with
nearly equivalent performance. Values for IDQ1,2 and IDQ3 shown have been optimized for CDMA operation. IDQ1, 2 and IDQ3 or IDQTOTAL can be adjusted to optimize the linearity of the amplifier for other modulation systems.

The device requires external input and output matching to as shown in Figure 3 and the Parts List.
2004 Fairchild Semiconductor Corporation

RMBA19500A

Application Information

CAUTION THIS IS AN ESD SENSITIVE DEVICE

The following describes a procedure for evaluating the RMBA19500A, a monolithic high efficiency power amplifier, in a surface mount package, designed for use as a driver stage for PCS1900 Base station or as the final output stage for Microand Pico-Cell base stations. Figure 1 shows the package outline and the pin designations. Figure 2 shows the functional block diagram of the packaged product. The RMBA19500A requires external passive components for DC bias and RF input and output matching circuits as shown in Figure 3 and the Parts List. A recommended schematic circuit is shown in Figure The gate biases for the three stages of the amplifier may be set by simple resistive voltage dividers. Figure 4 shows a typical layout of an evaluation board, corresponding to the schematic circuits of Figure The following designations should be noted:
1 Pin designations are as shown in Figure
2 Vg1, Vg2, and Vg3 are the Gate Voltages negative applied at the pins of the package.
3 Vgg1, 2, and Vgg3 are the negative supply voltages at the evaluation board terminals Vg1 and Vg2 are tied together .
4 Vd1, Vd2, and Vd3 are the Drain Voltages positive applied at the pins of the package.
5 Vdd is the positive supply voltage at the evaluation board terminal Vd1, Vd2, and Vd3 are tied together .

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Datasheet ID: RMBA19500A 634677