TLE4473GV55AUMA1

TLE4473GV55AUMA1 Datasheet

TLE 4473 GV55

Part	Datasheet
TLE4473GV55AUMA1	TLE4473GV55AUMA1 (pdf)

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Dual Low Drop Voltage Regulator TLE 4473 GV55 • Stand-by output 190 mA 5 V ± 2% • Main output 300 mA, 5 V tracked to the stand-by output • Low quiescent current consumption • Disable function separately for both outputs • Wide operation range up to 42 V • Very low dropout voltage • 2 independent reset circuits • Watchdog • Output protected against short circuit • Wide temperature range -40 °C to 150 °C • Overtemperature protection • Overload protection P-DSO-12-2, -3, -6 Functional Description The TLE 4473 is a monolithic integrated voltage regulator with two very low drop outputs, a main output Q1 for loads up to 300 mA and a stand by output Q2 providing a maximum of 190 mA. The stand-by regulator transforms an input voltage VI in the range of V VI 42 V to VQ2 = V ±2% output voltage. The main output is tracked to the stand by output voltage and provides also 5 V. Versions of the device with 5 V/3.3 V and 5 V/2.6 V are available, please refer to the data sheet TLE 4473 G V53/TLE 4473 G V52. Two Inhibit Pins allow to use either both output voltages or to disable only Q1 or to switch off both outputs, the latter causing the current consumption to drop below 1 µA. The TLE 4473 is designed to supply microprocessor systems and sensors under the severe conditions of automotive applications and is therefore equipped with additional protection functions against overload, short circuit and overtemperature. The device operates in the wide junction temperature range of -40 °C to 150 °C. Type TLE 4473 GV55 Data Sheet Ordering Code Q67007-A9647 Package P-DSO-12-6 TLE 4473 GV55 The device features a reset with adjustable power on delay for each of the outputs. In addition the output for the microcontroller supply comes up with a watchdog in order to supervise a connected microcontroller Reset and Watchdog Behavior The reset output RO2 is in high-state if the voltage on the delay capacitor CD2 is greater or equal VDU2. The delay capacitor CD2 is charged with the current IDC2 for output voltages greater than the reset threshold VRT2. If the output voltage gets lower than VRT2 ‘reset condition’ a fast discharge of the delay capacitor CD2 sets in and as soon as VD2 gets lower than VDL2 the reset output RO2 is set to low-level. The time for the delay capacitor charge is the reset delay time. For the power-on case the charging process of CD2 starts from 0 V, which leads to the equation: tD, on C-----D---2----x-----V----D---U----2 IDC2 for the power-on reset delay time. When the voltage on the delay capacitor has reached VDU2 and reset was set to high, the watchdog circuit is enabled and discharges CD2 with the constant current IDD2. If there is no rising edge observed at the watchdog input, CD2 will be discharge down to VDL2. Then reset output RO2 will be set to low and CD2 will be charged again with the current IDC2 until VD2 reaches VDU2 and reset will be set high again. If the watchdog pulse rising edge at watchdog input WI occurs during the discharge period CD2 is charged again and the reset output stays high. After VD2 has reached VDU2, the periodical cycle starts again. The watchdog timing is shown in Figure The maximum duration between two watchdog pulses corresponds to the minimum watchdog trigger time TWI,tr. Higher capacitances on pin D2 result in longer watchdog trigger times: TWI,tr max = ms/nF x CD2 If the output voltage Q1 decreases below VRT1 typ. V , the external capacitor CD1 is discharged by the reset generator of the main output. If the voltage on this capacitor drops below VDL1, a reset signal is generated on pin 2 RO1 . If the output voltage rises above the reset threshold, CD1 will be charged with the constant current IDC1. After the power-on-reset time the voltage on the capacitor reaches VDU1 and the reset output will be set high again. The value of the power-on-reset time can be set within a wide range depending of the capacitance of CD1 using the above given equation 1 analogous for Data Sheet TLE 4473 GV55 VWΙ TWD, p VDU2 VDL2 VRO2 TWI, tr t WD, L TWI, VDU2 -VDL2 C D2; TWD, VDU2 -VDL2 Ι DC2

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Dual Low Drop Voltage Regulator

TLE 4473 GV55
• Stand-by output 190 mA 5 V ± 2%
• Main output 300 mA, 5 V tracked to the stand-by
output
• Low quiescent current consumption
• Disable function separately for both outputs
• Wide operation range up to 42 V
• Very low dropout voltage
• 2 independent reset circuits
• Watchdog
• Output protected against short circuit
• Wide temperature range -40 °C to 150 °C
• Overtemperature protection
• Overload protection

P-DSO-12-2, -3, -6

Functional Description

The TLE 4473 is a monolithic integrated voltage regulator with two very low drop outputs, a main output Q1 for loads up to 300 mA and a stand by output Q2 providing a maximum
of 190 mA. The stand-by regulator transforms an input voltage VI in the range of V VI 42 V to VQ2 = V ±2% output voltage. The main output is tracked to the stand by
output voltage and provides also 5 V. Versions of the device with 5 V/3.3 V and 5 V/2.6 V are available, please refer to the data sheet TLE 4473 G V53/TLE 4473 G V52. Two Inhibit Pins allow to use either both output voltages or to disable only Q1 or to switch off both outputs, the latter causing the current consumption to drop below 1 µA. The TLE 4473 is designed to supply microprocessor systems and sensors under the severe conditions of automotive applications and is therefore equipped with additional protection functions against overload, short circuit and overtemperature. The device operates in the wide junction temperature range of -40 °C to 150 °C.

Type TLE 4473 GV55

Data Sheet
Ordering Code Q67007-A9647

Package P-DSO-12-6

TLE 4473 GV55

The device features a reset with adjustable power on delay for each of the outputs. In addition the output for the microcontroller supply comes up with a watchdog in order to supervise a connected microcontroller

Reset and Watchdog Behavior

The reset output RO2 is in high-state if the voltage on the delay capacitor CD2 is greater or equal VDU2. The delay capacitor CD2 is charged with the current IDC2 for output voltages greater than the reset threshold VRT2. If the output voltage gets lower than VRT2 ‘reset condition’ a fast discharge of the delay capacitor CD2 sets in and as soon as VD2 gets lower than VDL2 the reset output RO2 is set to low-level. The time for the delay
capacitor charge is the reset delay time. For the power-on case the charging process of

CD2 starts from 0 V, which leads to the equation:
tD, on

C-----D---2----x-----V----D---U----2 IDC2
for the power-on reset delay time.

When the voltage on the delay capacitor has reached VDU2 and reset was set to high, the watchdog circuit is enabled and discharges CD2 with the constant current IDD2.

If there is no rising edge observed at the watchdog input, CD2 will be discharge down to VDL2. Then reset output RO2 will be set to low and CD2 will be charged again with the current IDC2 until VD2 reaches VDU2 and reset will be set high again.

If the watchdog pulse rising edge at watchdog input WI occurs during the discharge
period CD2 is charged again and the reset output stays high. After VD2 has reached VDU2,
the periodical cycle starts again.

The watchdog timing is shown in Figure The maximum duration between two
watchdog pulses corresponds to the minimum watchdog trigger time TWI,tr. Higher
capacitances on pin D2 result in longer watchdog trigger times:

TWI,tr max = ms/nF x CD2

If the output voltage Q1 decreases below VRT1 typ. V , the external capacitor CD1
is discharged by the reset generator of the main output. If the voltage on this capacitor
drops below VDL1, a reset signal is generated on pin 2 RO1 . If the output voltage rises above the reset threshold, CD1 will be charged with the constant current IDC1. After the power-on-reset time the voltage on the capacitor reaches VDU1 and the reset output will
be set high again. The value of the power-on-reset time can be set within a wide range
depending of the capacitance of CD1 using the above given equation 1 analogous for

Data Sheet

TLE 4473 GV55

VWΙ

TWD, p

VDU2 VDL2

VRO2

TWI, tr
t WD, L

TWI,

VDU2
-VDL2

C D2;

TWD,

VDU2
-VDL2
Ι DC2

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Datasheet ID: TLE4473GV55AUMA1 638754