NDC631N

NDC631N Datasheet

NDC631N N-Channel Logic Level Enhancement Mode Field Effect Transistor

Part	Datasheet
NDC631N	NDC631N (pdf)

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NDC631N N-Channel Logic Level Enhancement Mode Field Effect Transistor July 1996 These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMICA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package. A, 20 V. RDS ON = VGS = V RDS ON = VGS V. Proprietary SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS ON . Exceptional on-resistance and maximum DC current capability. Absolute Maximum Ratings TA = 25°C unless otherwise note Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage - Continuous Drain Current - Continuous - Pulsed Note 1a Maximum Power Dissipation Note 1a Note 1b Note 1c TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case Note 1a Note 1 NDC631N 20 8 15 1 -55 to 150 78 30 Units V A °C/W °C/W 1997 Fairchild Semiconductor Corporation ELECTRICAL CHARACTERISTICS TA = 25°C unless otherwise noted Symbol Parameter Conditions OFF CHARACTERISTICS BVDSS IDSS Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 µA VDS = 16 V, VGS = 0 V IGSSF Gate - Body Leakage, Forward IGSSR ON CHARACTERISTICS Note 2 VGS th Gate Threshold Voltage VGS = 8 V, VDS = 0 V VGS = -8 V, VDS= 0 V

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NDC631N N-Channel Logic Level Enhancement Mode Field Effect Transistor

July 1996

These N-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMICA cards, and other battery powered circuits where fast switching, and low in-line power loss are needed in a very small outline surface mount package.

A, 20 V. RDS ON = VGS = V RDS ON = VGS V.

Proprietary SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities.

High density cell design for extremely low RDS ON .

Exceptional on-resistance and maximum DC current capability.

Absolute Maximum Ratings TA = 25°C unless otherwise note Symbol Parameter

VDSS

Drain-Source Voltage

VGSS

Gate-Source Voltage - Continuous

Drain Current - Continuous
- Pulsed

Note 1a

Maximum Power Dissipation

Note 1a

Note 1b Note 1c

TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case

Note 1a Note 1

NDC631N 20 8 15 1
-55 to 150
78 30

Units V A
°C/W °C/W
1997 Fairchild Semiconductor Corporation

ELECTRICAL CHARACTERISTICS TA = 25°C unless otherwise noted

Symbol Parameter

Conditions

OFF CHARACTERISTICS

BVDSS IDSS

Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current

VGS = 0 V, ID = 250 µA VDS = 16 V, VGS = 0 V

IGSSF

Gate - Body Leakage, Forward

IGSSR

ON CHARACTERISTICS Note 2

VGS th

Gate Threshold Voltage

VGS = 8 V, VDS = 0 V VGS = -8 V, VDS= 0 V

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Datasheet ID: NDC631N 634589