MM74HC597N

MM74HC597N Datasheet

MM74HC597 8-Bit Shift Registers with Input Latches

Part	Datasheet
MM74HC597N	MM74HC597N (pdf)

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MM74HC597 8-Bit Shift Registers with Input Latches MM74HC597 8-Bit Shift Registers with Input Latches This high speed register utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 10 LS-TTL loads. The MM74HC597 comes in a 16-pin package and consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and shift register have positive-edge triggered clocks. the shift register also has direct load from storage and clear inputs. The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. s 8-bit parallel storage register inputs s Wide operating voltage range s Shift register has direct overriding load and clear s Guaranteed shift frequency DC to 30 MHz s Low quiescent current 80 µA maximum Ordering Code: Order Number Package Number Package Description MM74HC597M Note 1 M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow MM74HC597SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide MM74HC597N N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Note 1 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Top View RCK SCK SLOAD SCLR Function X Data Loaded to input latches Data loaded from inputs to H shift register Data transferred from clock X H input latches to shift edge register Invalid logic, state of L shift register indeterminate when signals removed L Shift register cleared Shift register clocked H Qn = Qn−1, Q0 = SER 2004 Fairchild Semiconductor Corporation DS005343 MM74HC597 Functional Block Diagram Positive Logic Timing Diagram MM74HC597 Absolute Maximum Ratings Note 2 Note 3 Supply Voltage VCC to +7.0V DC Input Voltage VIN to VCC+1.5V DC Output Voltage VOUT to VCC+0.5V Clamp Diode Current IIK, IOK ±20 mA DC Output Current, per pin IOUT ±25 mA DC VCC or GND Current, per pin ICC ±70 mA Storage Temperature Range TSTG −65°C to +150°C Power Dissipation PD Note 4

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MM74HC597 8-Bit Shift Registers with Input Latches

MM74HC597 8-Bit Shift Registers with Input Latches

This high speed register utilizes advanced silicon-gate CMOS technology. It has the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 10 LS-TTL loads.

The MM74HC597 comes in a 16-pin package and consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and shift register have positive-edge triggered clocks. the shift register also has direct load from storage and clear inputs.

The 74HC logic family is speed, function, and pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
s 8-bit parallel storage register inputs s Wide operating voltage range s Shift register has direct overriding load and clear s Guaranteed shift frequency DC to 30 MHz s Low quiescent current 80 µA maximum
Ordering Code:

Order Number Package Number

Package Description

MM74HC597M Note 1

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

MM74HC597SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide

MM74HC597N

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Note 1 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Truth Table

Top View

RCK SCK SLOAD SCLR

Function

X Data Loaded to input latches

Data loaded from inputs to H
shift register

Data transferred from
clock X

H input latches to shift
edge
register

Invalid logic, state of

L shift register indeterminate
when signals removed

L Shift register cleared

Shift register clocked H

Qn = Qn−1, Q0 = SER
2004 Fairchild Semiconductor Corporation DS005343

MM74HC597

Functional Block Diagram Positive Logic Timing Diagram

MM74HC597

Absolute Maximum Ratings Note 2

Note 3

Supply Voltage VCC
to +7.0V

DC Input Voltage VIN
to VCC+1.5V

DC Output Voltage VOUT
to VCC+0.5V

Clamp Diode Current IIK, IOK
±20 mA

DC Output Current, per pin IOUT
±25 mA

DC VCC or GND Current, per pin ICC
±70 mA

Storage Temperature Range TSTG −65°C to +150°C

Power Dissipation PD

Note 4

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Datasheet ID: MM74HC597N 634395