MM74HC4514N

MM74HC4514N Datasheet

MM74HC4514 4-to-16 Line Decoder with Latch

Part	Datasheet
MM74HC4514N	MM74HC4514N (pdf)

Related Parts	Information
MM74HC4514MTC	MM74HC4514MTC
MM74HC4514WMX	MM74HC4514WMX
MM74HC4514WM	MM74HC4514WM
MM74HC4514MTCX	MM74HC4514MTCX

PDF Datasheet Preview
MM74HC4514 4-to-16 Line Decoder with Latch MM74HC4514 4-to-16 Line Decoder with Latch The MM74HC4514 utilizes advanced silicon-gate CMOS technology, which is well suited to memory address decoding or data routing application. It possesses high noise immunity and low power dissipation usually associated with CMOS circuitry, yet speeds comparable to low power Schottky TTL circuits. It can drive up to 10 LS-TTL loads. The MM74HC4514 contain a 4-to-16 line decoder and a 4bit latch. The latch can store the data on the select inputs, thus allowing a selected output to remain HIGH even though the select data has changed. When the LATCH ENABLE input to the latches is HIGH the outputs will change with the inputs. When LATCH ENABLE goes LOW the data on the select inputs is stored in the latches. The four select inputs determine which output will go HIGH provided the INHIBIT input is LOW. If the INHIBIT input is HIGH all outputs are held LOW thus disabling the decoder. The MM74HC4514 is functionally and pinout equivalent to the CD4514BC and the MC1451BC. All inputs are protected against damage due to static discharge diodes from VCC and ground. s Typical propagation delay 18 ns s Low quiescent power 80 µA maximum 74HC Series s Low input current 1 µA maximum s Fanout of 10 LS-TTL loads 74HC Series Ordering Code: Order Number Package Number Package Description MM74HC4514WM M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide MM74HC4514MTC MTC24 24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide MM74HC4514N N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2003 Fairchild Semiconductor Corporation DS005215 MM74HC4514 Connection Diagram Top View Logic Diagram Truth Table LE Inhibit Data Inputs D C B A Selected Output High LLLL L LHL L LHH LHL L LHLH L HH L L HHH HLLH HLHL H LHH HHL L HH L H HHHL HHHH X Outputs = 0 Latched XXXX Data MM74HC4514 Absolute Maximum Ratings Note 1 Note 2 Supply Voltage VCC DC Input Voltage VIN DC Output Voltage VOUT Clamp Diode Current IIK, IOK DC Output Current, per pin IOUT DC VCC or GND Current, per pin ICC Storage Temperature Range TSTG Power Dissipation PD Note 3 S.O. Package only Lead Temperature TL Soldering 10 seconds to +7.0V to VCC +1.5V to VCC +0.5V ±20 mA ±25 mA ±50 mA −65°C to +150°C 600 mW 500 mW 260°C Recommended Operating Conditions Min Max Units

PDF Datasheet Preview

MM74HC4514 4-to-16 Line Decoder with Latch

MM74HC4514 4-to-16 Line Decoder with Latch

The MM74HC4514 utilizes advanced silicon-gate CMOS technology, which is well suited to memory address decoding or data routing application. It possesses high noise immunity and low power dissipation usually associated with CMOS circuitry, yet speeds comparable to low power Schottky TTL circuits. It can drive up to 10 LS-TTL loads.

The MM74HC4514 contain a 4-to-16 line decoder and a 4bit latch. The latch can store the data on the select inputs, thus allowing a selected output to remain HIGH even though the select data has changed. When the LATCH ENABLE input to the latches is HIGH the outputs will change with the inputs. When LATCH ENABLE goes LOW the data on the select inputs is stored in the latches. The four select inputs determine which output will go HIGH provided the INHIBIT input is LOW. If the INHIBIT input is HIGH all outputs are held LOW thus disabling the decoder.

The MM74HC4514 is functionally and pinout equivalent to the CD4514BC and the MC1451BC. All inputs are protected against damage due to static discharge diodes from VCC and ground.
s Typical propagation delay 18 ns s Low quiescent power 80 µA maximum 74HC Series s Low input current 1 µA maximum s Fanout of 10 LS-TTL loads 74HC Series
Ordering Code:

Order Number Package Number

Package Description

MM74HC4514WM

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide

MM74HC4514MTC

MTC24
24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide

MM74HC4514N

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2003 Fairchild Semiconductor Corporation DS005215

MM74HC4514

Connection Diagram

Top View

Logic Diagram

Truth Table

LE Inhibit

Data Inputs

D C B A Selected Output High

LLLL

L LHL

L LHH

LHL L

LHLH

L HH L

L HHH

HLLH

HLHL

H LHH

HHL L

HH L H

HHHL

HHHH

X Outputs = 0

Latched

XXXX

Data

MM74HC4514

Absolute Maximum Ratings Note 1

Note 2

Supply Voltage VCC DC Input Voltage VIN DC Output Voltage VOUT Clamp Diode Current IIK, IOK DC Output Current, per pin IOUT DC VCC or GND Current, per pin ICC Storage Temperature Range TSTG Power Dissipation PD

Note 3

S.O. Package only

Lead Temperature TL Soldering 10 seconds
to +7.0V to VCC +1.5V to VCC +0.5V
±20 mA ±25 mA ±50 mA −65°C to +150°C
600 mW 500 mW
260°C

Recommended Operating Conditions

Min Max Units

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Datasheet ID: MM74HC4514N 634391