MM74HC139N

MM74HC139N Datasheet

MM74HC139 Dual 2-To-4 Line Decoder

Part	Datasheet
MM74HC139N	MM74HC139N (pdf)

Related Parts	Information
MM74HC139M	MM74HC139M

PDF Datasheet Preview
MM74HC139 Dual 2-To-4 Line Decoder MM74HC139 Dual 2-To-4 Line Decoder The MM74HC139 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications. It possesses the high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic. The MM74HC139 contain two independent one-of-four decoders each with a single active low enable input G1, or G2 . Data on the select inputs A1, and B1 or A2, and B2 cause one of the four normally high outputs to go LOW. The decoder’s outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally as well as pin equivalent to the 74LS139. All inputs are protected from damage due to static discharge by diodes to VCC and ground. s Typical propagation delays Select to outputs 4 delays 18 ns Select to output 5 delays 28 ns Enable to output 20 ns s Low power 40 µW quiescent supply power s Fanout of 10 LS-TTL devices s Input current maximum 1 µA, typical 10 pA Ordering Code: Order Number Package Number Package Description MM74HC139M Note 1 M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow MM74HC139SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide MM74HC139MTC Note 1 MTC16 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide MM74HC139N N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Note 1 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Inputs Enable Select H = HIGH Level L = LOW Level X = Don't Care Outputs Y0 Y1 Y2 Y3 HHHH L HHH H LHH HH L H HHHL 2003 Fairchild Semiconductor Corporation DS005311 MM74HC139 Logic Diagram 1 of 2 MM74HC139 Absolute Maximum Ratings Note 2 Note 3 Recommended Operating Conditions Supply Voltage VCC DC Input Voltage VIN DC Output Voltage VOUT Clamp Diode Current IIK, IOK DC Output Current, per pin IOUT DC VCC or GND Current, per pin ICC Storage Temperature Range TSTG Power Dissipation PD Note 4 S.O. Package only Lead Temperature TL Soldering 10 seconds to +7.0V to VCC +1.5V to VCC +0.5V ±20 mA ±25 mA ±50 mA −65°C to +150°C 600 mW 500 mW 260°C Min Max Units Supply Voltage VCC DC Input or Output Voltage VIN, VOUT Operating Temperature Range TA −40 +85 Input Rise or Fall Times tr, tf VCC = 2.0V 1000 ns VCC = 4.5V VCC = 6.0V Note 2 Absolute Maximum Ratings are those values beyond which dam- age to the device may occur. Note 3 Unless otherwise specified all voltages are referenced to ground. Note 4 Power Dissipation temperature derating plastic “N” package − 12 mW/°C from 65°C to 85°C. DC Electrical Characteristics Note 5 Parameter Conditions

PDF Datasheet Preview

MM74HC139 Dual 2-To-4 Line Decoder

MM74HC139 Dual 2-To-4 Line Decoder

The MM74HC139 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications. It possesses the high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic.

The MM74HC139 contain two independent one-of-four decoders each with a single active low enable input G1, or G2 . Data on the select inputs A1, and B1 or A2, and B2 cause one of the four normally high outputs to go LOW.

The decoder’s outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally as well as pin equivalent to the 74LS139. All inputs are protected from damage due to static discharge by diodes to VCC and ground.
s Typical propagation delays Select to outputs 4 delays 18 ns Select to output 5 delays 28 ns Enable to output 20 ns
s Low power 40 µW quiescent supply power s Fanout of 10 LS-TTL devices s Input current maximum 1 µA, typical 10 pA
Ordering Code:

Order Number Package Number

Package Description

MM74HC139M Note 1

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

MM74HC139SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide

MM74HC139MTC Note 1

MTC16
16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide

MM74HC139N

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Note 1 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Truth Table

Inputs

Enable Select

H = HIGH Level L = LOW Level X = Don't Care

Outputs

Y0 Y1 Y2 Y3 HHHH L HHH H LHH HH L H HHHL
2003 Fairchild Semiconductor Corporation DS005311

MM74HC139

Logic Diagram
1 of 2

MM74HC139

Absolute Maximum Ratings Note 2

Note 3

Recommended Operating Conditions

Supply Voltage VCC DC Input Voltage VIN DC Output Voltage VOUT Clamp Diode Current IIK, IOK DC Output Current, per pin IOUT DC VCC or GND Current, per pin ICC Storage Temperature Range TSTG Power Dissipation PD

Note 4

S.O. Package only

Lead Temperature TL Soldering 10 seconds
to +7.0V to VCC +1.5V to VCC +0.5V
±20 mA ±25 mA ±50 mA −65°C to +150°C
600 mW 500 mW
260°C

Min Max Units

Supply Voltage VCC

DC Input or Output Voltage

VIN, VOUT

Operating Temperature Range TA −40 +85

Input Rise or Fall Times
tr, tf VCC = 2.0V
1000 ns

VCC = 4.5V

VCC = 6.0V

Note 2 Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.

Note 3 Unless otherwise specified all voltages are referenced to ground.

Note 4 Power Dissipation temperature derating plastic “N” package − 12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics Note 5

Parameter

Conditions

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Datasheet ID: MM74HC139N 634371