MM74C165N

MM74C165N Datasheet

MM74C165 Parallel-Load 8-Bit Shift Register

Part	Datasheet
MM74C165N	MM74C165N (pdf)

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MM74C165 Parallel-Load 8-Bit Shift Register MM74C165 Parallel-Load 8-Bit Shift Register The MM74C165 functions as an 8-bit parallel-load, serial shift register. Data is loaded into the register independent of the state of the clock s when PARALLEL LOAD PL is low. Shifting is inhibited as long as PL is low. Data is sequentially shifted from complementary outputs, Q7 and Q7, highest-order bit P7 first. New serial data may be entered via the SERIAL DATA Ds input. Serial shifting occurs on the rising edge of CLOCK1 or CLOCK2. Clock inputs may be used separately or together for combined clocking from independent sources. Either clock input may be used also as an active-low clock enable. To prevent double-clocking when a clock input is used as an enable, the enable must be changed to a high level disabled only while the clock is HIGH. s Wide supply voltage range 3V to 15V s Guaranteed noise margin 1V s High noise immunity VCC typ. s Low power TTL compatibility fan out of 2 driving 74L s Parallel loading independent of clock s Dual clock inputs s Fully static operation Ordering Code: Order Number Package Number Package Description MM74165N N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Connection Diagram Top View 2002 Fairchild Semiconductor Corporation DS005897 MM74C165 Block Diagrams *Please look into Section 8, Appendix D for availability of various package types. Truth Table State Inputs Internal PL Clock1 Clock2 Ds P0 thru P7 Q0 Q1 as enable Parallel Load L X P0 P1 Enable P0 P1 Shift with Ds H Shift with Ds H Hold Disable H X = Don’t Care H = VIN 1 L = VIN 0 = Clock transition from VIN 0 to VIN 1 P0 thru P7 = Data present and loaded into parallel inputs Q0 thru Q6 = Internal flip-flop outputs Outputs Q7 P7 P6 P5 MM74C165 Absolute Maximum Ratings Note 1 Voltage at Any Pin Operating Temperature Range Storage Temperature Range Absolute Maximum VCC Power Dissipation Dual-In-Line Small Outline Operating VCC Range Lead Temperature Soldering, 10 seconds −0.3V to VCC + 0.3V −55°C to +125°C −65°C to +150°C 18V 700 mW 500 mW 3V to 15V 260°C Note 1 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions for actual device operation. DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted Parameter Conditions CMOS TO CMOS VIN 1

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MM74C165 Parallel-Load 8-Bit Shift Register

MM74C165 Parallel-Load 8-Bit Shift Register

The MM74C165 functions as an 8-bit parallel-load, serial shift register. Data is loaded into the register independent of the state of the clock s when PARALLEL LOAD PL is low. Shifting is inhibited as long as PL is low. Data is sequentially shifted from complementary outputs, Q7 and Q7, highest-order bit P7 first. New serial data may be entered via the SERIAL DATA Ds input. Serial shifting occurs on the rising edge of CLOCK1 or CLOCK2. Clock inputs may be used separately or together for combined clocking from independent sources. Either clock input may be used also as an active-low clock enable. To prevent double-clocking when a clock input is used as an enable, the enable must be changed to a high level disabled only while the clock is HIGH.
s Wide supply voltage range 3V to 15V s Guaranteed noise margin 1V s High noise immunity VCC typ. s Low power TTL compatibility fan out of 2 driving 74L s Parallel loading independent of clock s Dual clock inputs s Fully static operation
Ordering Code:

Order Number Package Number

Package Description

MM74165N

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

Connection Diagram

Top View
2002 Fairchild Semiconductor Corporation DS005897

MM74C165

Block Diagrams
*Please look into Section 8, Appendix D for availability of various package types.

Truth Table

State

Inputs

Internal

PL Clock1 Clock2 Ds P0 thru P7 Q0 Q1 as enable

Parallel Load L

X P0 P1

Enable

P0 P1

Shift with Ds H

Shift with Ds H

Hold Disable H

X = Don’t Care H = VIN 1 L = VIN 0 = Clock transition from VIN 0 to VIN 1 P0 thru P7 = Data present and loaded into parallel inputs Q0 thru Q6 = Internal flip-flop outputs

Outputs Q7

P7 P6 P5

MM74C165

Absolute Maximum Ratings Note 1

Voltage at Any Pin Operating Temperature Range Storage Temperature Range Absolute Maximum VCC Power Dissipation

Dual-In-Line Small Outline Operating VCC Range Lead Temperature Soldering, 10 seconds
−0.3V to VCC + 0.3V −55°C to +125°C −65°C to +150°C 18V
700 mW 500 mW 3V to 15V
260°C

Note 1 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions for actual device operation.

DC Electrical Characteristics

Min/Max limits apply across temperature range unless otherwise noted

Parameter

Conditions

CMOS TO CMOS

VIN 1

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Datasheet ID: MM74C165N 634346