FA80486GXSF33

FA80486GXSF33 Datasheet

Product FA80486GXSF-33

Part	Datasheet
FA80486GXSF33	FA80486GXSF33 (pdf)

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EMBEDDED ULTRA-LOW POWER Intel486 GX PROCESSOR • Ultra-Low Power Member of the Intel486 • 16-Bit External Data Bus Processor Family 32-Bit RISC Technology Core 8-Kbyte Write-Through Cache Four Internal Write Buffers • 176-Lead Thin Quad Flat Pack TQFP • Separate Voltage Supply for Core Circuitry • Fast Core-Clock Restart Burst Bus Cycles • Auto Clock Freeze Data Bus Parity Generation and • Ideal for Embedded Battery-Operated and Checking Hand-Held Applications Intel System Management Mode SMM Boundary Scan JTAG Barrel Shifter Register File Base/ Index Bus 64-Bit Interunit Transfer Bus 32-Bit Data Bus 32-Bit Data Bus Linear Address Segmentation Unit Descriptor Registers Limit and Attribute PLA Paging Unit PCD PWT Translation Lookaside Buffer Physical Address Cache Unit 8 Kbyte Cache Core Clock Clock Control CLK Input Bus Interface Address Drivers Write Buffers 4 x 32 Data Bus 32 Transceivers A31-A2 BE3#- BE0# D15-D0 MicroInstruction Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at Copyright Intel Corporation, 1997 *Third-party brands and names are the property of their respective owners. Contents Embedded Ultra-Low Power Intel486 GX Processor INTRODUCTION 1 Features 1 Family Members 3 HOW TO USE THIS DOCUMENT 3 PIN DESCRIPTIONS 3 Pin Assignments 3 Pin Quick Reference 7 ARCHITECTURAL AND FUNCTIONAL OVERVIEW 15 Separate Supply Voltages 15 Fast Clock Restart 16 Level-Keeper Circuits 17 Low-Power Features 18 Auto Clock Freeze 18 Bus Interface and Operation 19 16-Bit Data Bus 19 Parity 19 Data Transfer Mechanism 19 CPUID Instruction 27 Operation of the CPUID Instruction 27 Identification After Reset 29 Boundary Scan JTAG 29 Device Identification 29 Boundary Scan Register Bits and Bit Order 29 ELECTRICAL SPECIFICATIONS 30 Maximum Ratings 30 DC Specifications 30 AC Specifications 34 Capacitive Derating Curves 41 MECHANICAL DATA 42 Package Dimensions 42 Package Thermal Specifications 43 FIGURES Figure Embedded Ultra-Low Power Intel486 GX Processor Block Diagram i Package Diagram for 176-Lead TQFP Package Embedded ULP Intel486 GX Processor 4 Example of Supply Voltage Power Sequence 16 Stop Clock State Diagram with Typical Power Consumption Values 17 Logic to Generate A1, BHE# and BLE# 19 Contents Figure Figure Figure Address Prediction for Burst Transfers 1 of 3 25 Address Prediction for Burst Transfers 2 of 3 26 Address Prediction for Burst Transfers 3 of 3 27 CLK Waveform 37 Input Setup and Hold Timing 37 Input Setup and Hold Timing 38 Output Valid Delay Timing 38 PCHK# Valid Delay Timing 39 Maximum Float Delay Timing 39 TCK Waveform 40 Test Signal Timing Diagram 40 Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Low-to-High Transition 41 Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a High-to-Low Transition 41 Package Mechanical Specifications for the 176-Lead TQFP Package 42 TABLES Table Table The Embedded Ultra-Low Power Intel486 GX Processor 3 Pin Assignment for 176-Lead TQFP Package Embedded ULP Intel486 GX Processor 5 Pin Cross Reference for 176-Lead TQFP Package Embedded ULP Intel486 GX Processor 6 Embedded ULP Intel486 GX Processor Pin Descriptions 7 Output Pins 13 Input/Output Pins 13 Test Pins 14 Input Pins 14 Valid Byte-Enable Cycles 20 Address Sequence for Cache Line Transfers and Instruction Prefetches 22 Valid Burst Cycle Sequences - I/O Reads and All Writes 23 CPUID Instruction Description 28 Boundary Scan Component Identification Code 29 Absolute Maximum Ratings 30 Operating Supply Voltages 31 DC Specifications 31 Active ICC Values 32 Clock Stop, Stop Grant, and Auto HALT Power Down ICC Values 33 AC Characteristics 34 AC Specifications for the Test Access Port 36 Thermal Resistance 43 Maximum Ambient Temperature TA 43 Embedded Ultra-Low Power Intel486 GX Processor INTRODUCTION This data sheet describes the embedded Ultra-Low Power ULP Intel486 GX processor. It is intended for embedded battery-operated and hand-held applications. The embedded ULP Intel486 GX processor provides all of the features of the Intel486 SX processor except for the 8-bit bus sizing logic and the processor-upgrade pin. The processor typically uses 20% to 50% less power than the Intel486 SX processor. Additionally, the embedded ULP Intel486 GX processor external data bus and parity signals have level-keeper circuitry and a fast-recovery core clock which are vital for ultra-low-power system designs. The processor is available in a Thin Quad Flat Package TQFP enabling low-profile component implementation. The embedded ULP Intel486 GX processor consists of a 32-bit integer processing unit, an on-chip cache, and a memory management unit. The design ensures full instruction-set compatibility with the 8086, 8088, 80186, 80286, Intel386 SX, Intel386 DX, and all versions of Intel486 processors. The embedded ULP Intel486 GX processor offers these features of the Intel486 SX processor: • 32-bit RISC-Technology Core The embedded ULP Intel486 GX processor performs a complete set of arithmetic and logical operations on 8-, 16-, and 32-bit data types using a full-width ALU and eight general purpose registers. • Single Cycle Execution Many instructions execute in a single clock cycle. • Instruction Pipelining Overlapped instruction fetching, decoding, address translation and execution. • On-Chip Cache with Cache Consistency Support An 8-Kbyte, write-through, internal cache is used for both data and instructions. Cache hits provide zero wait-state access times for data within the cache. Bus activity is tracked to detect alterations in the memory represented by the internal cache. The internal cache can be invalidated or flushed so that an external cache controller can maintain cache consistency. • External Cache Control Write-back and flush controls for an external cache are provided so the processor can maintain cache consistency. • On-Chip Memory Management Unit Address management and memory space protection mechanisms maintain the integrity of memory in a multitasking and virtual memory environment. Both segmentation and paging are supported. • Burst Cycles Burst transfers allow a new 16-bit data word to be read from memory on each bus clock cycle. This capability is especially useful for instruction prefetch and for filling the internal cache. Burst transfers also occur on some memory write and some I/O data transfers. • Write Buffers The processor contains four write buffers to enhance the performance of consecutive writes to memory. The processor can continue internal operations after a write to these buffers, without waiting for the write to be completed on the external bus. • Bus Backoff When another bus master needs control of the bus during a processor initiated bus cycle, the embedded ULP Intel486 GX processor floats its bus signals, then restarts the cycle when the bus becomes available again. • Instruction Restart Programs can continue execution following an exception generated by an unsuccessful attempt to access memory. This feature is important for supporting demand-paged virtual memory applications. • Boundary Scan JTAG Boundary Scan provides in-circuit testing of components on printed circuit boards. The Intel Boundary Scan implementation conforms with the IEEE Standard Test Access Port and Boundary Scan Architecture. Embedded Ultra-Low Power Intel486 GX Processor • Intel System Management Mode SMM A unique Intel architecture operating mode provides a dedicated special purpose interrupt and address space that can be used to implement intelligent power management and other enhanced functions in a manner that is completely transparent to the operating system and applications software. • I/O Restart An I/O instruction interrupted by a System Management Interrupt SMI# can automatically be restarted following the execution of the RSM instruction. • Stop Clock The embedded ULP Intel486 GX processor has a stop clock control mechanism that provides two low-power states a Stop Grant state mW typical, depending on input clock frequency and a Stop Clock state ~60 µW typical, with input clock frequency of 0 MHz . • Auto HALT Power Down After the execution of a HALT instruction, the embedded ULP Intel486 GX processor issues a normal Halt bus cycle and the clock input to the processor core is automatically stopped, causing the processor to enter the Auto HALT Power Down state mW typical, depending on input clock frequency .

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EMBEDDED ULTRA-LOW POWER Intel486 GX PROCESSOR
• Ultra-Low Power Member of the Intel486
• 16-Bit External Data Bus

Processor Family 32-Bit RISC Technology Core 8-Kbyte Write-Through Cache Four Internal Write Buffers
• 176-Lead Thin Quad Flat Pack TQFP
• Separate Voltage Supply for Core Circuitry
• Fast Core-Clock Restart

Burst Bus Cycles
• Auto Clock Freeze

Data Bus Parity Generation and
• Ideal for Embedded Battery-Operated and

Checking

Hand-Held Applications

Intel System Management Mode SMM

Boundary Scan JTAG

Barrel Shifter

Register File

Base/ Index Bus
64-Bit Interunit Transfer Bus
32-Bit Data Bus
32-Bit Data Bus

Linear Address

Segmentation Unit

Descriptor Registers

Limit and Attribute PLA

Paging Unit

PCD PWT

Translation Lookaside

Buffer

Physical Address

Cache Unit
8 Kbyte Cache

Core Clock

Clock Control

CLK Input

Bus Interface

Address

Drivers

Write Buffers
4 x 32

Data Bus 32 Transceivers

A31-A2 BE3#- BE0#

D15-D0

MicroInstruction
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at

Copyright Intel Corporation, 1997
*Third-party brands and names are the property of their respective owners.

Contents

Embedded Ultra-Low Power Intel486 GX Processor

INTRODUCTION 1 Features 1 Family Members 3

HOW TO USE THIS DOCUMENT 3 PIN DESCRIPTIONS 3

Pin Assignments 3 Pin Quick Reference 7 ARCHITECTURAL AND FUNCTIONAL OVERVIEW 15 Separate Supply Voltages 15 Fast Clock Restart 16 Level-Keeper Circuits 17 Low-Power Features 18

Auto Clock Freeze 18 Bus Interface and Operation 19
16-Bit Data Bus 19 Parity 19 Data Transfer Mechanism 19 CPUID Instruction 27 Operation of the CPUID Instruction 27 Identification After Reset 29 Boundary Scan JTAG 29 Device Identification 29 Boundary Scan Register Bits and Bit Order 29 ELECTRICAL SPECIFICATIONS 30 Maximum Ratings 30 DC Specifications 30 AC Specifications 34 Capacitive Derating Curves 41 MECHANICAL DATA 42 Package Dimensions 42 Package Thermal Specifications 43

FIGURES Figure

Embedded Ultra-Low Power Intel486 GX Processor Block Diagram i Package Diagram for 176-Lead TQFP Package Embedded ULP Intel486 GX Processor 4 Example of Supply Voltage Power Sequence 16 Stop Clock State Diagram with Typical Power Consumption Values 17 Logic to Generate A1, BHE# and BLE# 19

Contents

Figure

Figure

Figure

Address Prediction for Burst Transfers 1 of 3 25 Address Prediction for Burst Transfers 2 of 3 26 Address Prediction for Burst Transfers 3 of 3 27 CLK Waveform 37 Input Setup and Hold Timing 37 Input Setup and Hold Timing 38 Output Valid Delay Timing 38 PCHK# Valid Delay Timing 39 Maximum Float Delay Timing 39 TCK Waveform 40 Test Signal Timing Diagram 40 Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a Low-to-High Transition 41 Typical Loading Delay versus Load Capacitance under Worst-Case Conditions for a High-to-Low Transition 41 Package Mechanical Specifications for the 176-Lead TQFP Package 42

TABLES Table

Table

The Embedded Ultra-Low Power Intel486 GX Processor 3 Pin Assignment for 176-Lead TQFP Package Embedded ULP Intel486 GX Processor 5 Pin Cross Reference for 176-Lead TQFP Package Embedded ULP Intel486 GX Processor 6 Embedded ULP Intel486 GX Processor Pin Descriptions 7 Output Pins 13 Input/Output Pins 13 Test Pins 14 Input Pins 14 Valid Byte-Enable Cycles 20 Address Sequence for Cache Line Transfers and Instruction Prefetches 22 Valid Burst Cycle Sequences - I/O Reads and All Writes 23 CPUID Instruction Description 28 Boundary Scan Component Identification Code 29 Absolute Maximum Ratings 30 Operating Supply Voltages 31 DC Specifications 31 Active ICC Values 32 Clock Stop, Stop Grant, and Auto HALT Power Down ICC Values 33 AC Characteristics 34 AC Specifications for the Test Access Port 36 Thermal Resistance 43 Maximum Ambient Temperature TA 43

Embedded Ultra-Low Power Intel486 GX Processor

INTRODUCTION

This data sheet describes the embedded Ultra-Low Power ULP Intel486 GX processor. It is intended for embedded battery-operated and hand-held applications. The embedded ULP Intel486 GX processor provides all of the features of the Intel486 SX processor except for the 8-bit bus sizing logic and the processor-upgrade pin. The processor typically uses 20% to 50% less power than the Intel486 SX processor. Additionally, the embedded ULP Intel486 GX processor external data bus and parity signals have level-keeper circuitry and a fast-recovery core clock which are vital for ultra-low-power system designs. The processor is available in a Thin Quad Flat Package TQFP enabling low-profile component implementation.

The embedded ULP Intel486 GX processor consists of a 32-bit integer processing unit, an on-chip cache, and a memory management unit. The design ensures full instruction-set compatibility with the 8086, 8088, 80186, 80286, Intel386 SX, Intel386 DX, and all versions of Intel486 processors.

The embedded ULP Intel486 GX processor offers these features of the Intel486 SX processor:
• 32-bit RISC-Technology Core The embedded ULP Intel486 GX processor performs a complete set of arithmetic and logical operations on 8-, 16-, and 32-bit data types using a full-width ALU and eight general purpose registers.
• Single Cycle Execution Many instructions execute in a single clock cycle.
• Instruction Pipelining Overlapped instruction fetching, decoding, address translation and execution.
• On-Chip Cache with Cache Consistency Support An 8-Kbyte, write-through, internal cache is used for both data and instructions. Cache hits provide zero wait-state access times for data within the cache. Bus activity is tracked to detect alterations in the memory represented by the internal cache. The internal cache can be invalidated or flushed so that an external cache controller can maintain cache consistency.
• External Cache Control Write-back and flush controls for an external cache are provided so the processor can maintain cache consistency.
• On-Chip Memory Management Unit Address management and memory space protection mechanisms maintain the integrity of memory in a multitasking and virtual memory environment. Both segmentation and paging are supported.
• Burst Cycles Burst transfers allow a new 16-bit data word to be read from memory on each bus clock cycle. This capability is especially useful for instruction prefetch and for filling the internal cache. Burst transfers also occur on some memory write and some I/O data transfers.
• Write Buffers The processor contains four write buffers to enhance the performance of consecutive writes to memory. The processor can continue internal operations after a write to these buffers, without waiting for the write to be completed on the external bus.
• Bus Backoff When another bus master needs control of the bus during a processor initiated bus cycle, the embedded ULP Intel486 GX processor floats its bus signals, then restarts the cycle when the bus becomes available again.
• Instruction Restart Programs can continue execution following an exception generated by an unsuccessful attempt to access memory. This feature is important for supporting demand-paged virtual memory applications.
• Boundary Scan JTAG Boundary Scan provides in-circuit testing of components on printed circuit boards. The Intel Boundary Scan implementation conforms with the IEEE Standard Test Access Port and Boundary Scan Architecture.

Embedded Ultra-Low Power Intel486 GX Processor
• Intel System Management Mode SMM A unique Intel architecture operating mode provides a dedicated special purpose interrupt and address space that can be used to implement intelligent power management and other enhanced functions in a manner that is completely transparent to the operating system and applications software.
• I/O Restart An I/O instruction interrupted by a System Management Interrupt SMI# can automatically be restarted following the execution of the RSM instruction.
• Stop Clock The embedded ULP Intel486 GX processor has a stop clock control mechanism that provides two low-power states a Stop Grant state mW typical, depending on input clock frequency and a Stop Clock state ~60 µW typical, with input clock frequency of 0 MHz .
• Auto HALT Power Down After the execution of a HALT instruction, the embedded ULP Intel486 GX processor issues a normal Halt bus cycle and the clock input to the processor core is automatically stopped, causing the processor to enter the Auto HALT Power Down state mW typical, depending on input clock frequency .

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Datasheet ID: FA80486GXSF33 638945