GTLP2T152M

GTLP2T152M Datasheet

GTLP2T152 2-Bit LVTTL/GTLP Transceiver

Part	Datasheet
GTLP2T152M	GTLP2T152M (pdf)

Related Parts	Information
GTLP2T152K8X	GTLP2T152K8X
GTLP2T152MX	GTLP2T152MX

PDF Datasheet Preview
GTLP2T152 2-Bit LVTTL/GTLP Transceiver GTLP2T152 2-Bit LVTTL/GTLP Transceiver The GTLP2T152 is a 2-bit transceiver that provides LVTTLto-GTLP signal level translation. Data directional control is handled with a transmit/receive pin. High-speed backplane operation is a direct result of GTLP’s reduced output swing <1V , reduced input threshold levels and output edge rate control. The edge rate control minimizes bus-settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic GTL JEDEC standard JESD8-3. Fairchild’s GTLP has internal edge-rate control and is process, voltage and temperature compensated. GTLP’s I/O structure is similar to GTL and BTL but offers different output levels and receiver threshold. Typical GTLP output voltage levels are VOL = 0.5V, VOH = 1.5V, and VREF = 1V. s Bidirectional interface between GTLP and LVTTL logic levels s Designed with edge rate control circuitry to reduce output noise on the GTLP port s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature s TTL compatible driver and control inputs s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s A Port source/sink −24mA/+24mA s B Port sink +50mA Ordering Code: Order Number GTLP2T152M GTLP2T152MX GTLP2T152K8X Package Number Package Description M08A 8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow [TUBE] M08A 8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow [TAPE and REEL] MAB08A 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide Preliminary [TAPE and REEL] Pin Descriptions Connection Diagrams Pin Names LVTTL Direction Control Receive Direction is Active LOW VCC, GND, VREF Device Supplies A Port LVTTL Input/Output B Port GTLP Input/Output US8 SOIC 2002 Fairchild Semiconductor Corporation DS500486 GTLP2T152 Functional Description The GTLP2T152 is a 2-bit transceiver that supports GTLP and LVTTL signal levels. Data polarity is non-inverting and the GTLP/LVTTL outputs are controlled by the T/R pin. Functional Table Inputs T/R H L Outputs Bus An Data to Bus Bn Bus Bn Data to Bus An Bn Output Data Enabled An Output Data Enabled Logic Diagram GTLP2T152 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Voltage VI DC Output Voltage VO Outputs 3-STATE Outputs Active Note 2 DC Output Sink Current into A Port IOL DC Output Source Current from A Port IOH DC Output Sink Current into B Port in the LOW State, IOL DC Input Diode Current IIK

PDF Datasheet Preview

GTLP2T152 2-Bit LVTTL/GTLP Transceiver

GTLP2T152 2-Bit LVTTL/GTLP Transceiver

The GTLP2T152 is a 2-bit transceiver that provides LVTTLto-GTLP signal level translation. Data directional control is handled with a transmit/receive pin. High-speed backplane operation is a direct result of GTLP’s reduced output swing <1V , reduced input threshold levels and output edge rate control. The edge rate control minimizes bus-settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic GTL JEDEC standard JESD8-3.

Fairchild’s GTLP has internal edge-rate control and is process, voltage and temperature compensated. GTLP’s I/O structure is similar to GTL and BTL but offers different output levels and receiver threshold. Typical GTLP output voltage levels are VOL = 0.5V, VOH = 1.5V, and VREF = 1V.
s Bidirectional interface between GTLP and LVTTL logic levels
s Designed with edge rate control circuitry to reduce output noise on the GTLP port
s VREF pin provides external supply reference voltage for receiver threshold adjustibility
s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature
s TTL compatible driver and control inputs s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs s Power up/down and power off high impedance for live
insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s A Port source/sink −24mA/+24mA s B Port sink +50mA
Ordering Code:

Order Number GTLP2T152M

GTLP2T152MX

GTLP2T152K8X

Package Number Package Description

M08A
8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow [TUBE]

M08A
8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow [TAPE and REEL]

MAB08A
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide

Preliminary [TAPE and REEL]

Pin Descriptions

Connection Diagrams

Pin Names

LVTTL Direction Control

Receive Direction is Active LOW

VCC, GND, VREF Device Supplies

A Port LVTTL Input/Output

B Port GTLP Input/Output

US8 SOIC
2002 Fairchild Semiconductor Corporation DS500486

GTLP2T152

Functional Description

The GTLP2T152 is a 2-bit transceiver that supports GTLP and LVTTL signal levels. Data polarity is non-inverting and the GTLP/LVTTL outputs are controlled by the T/R pin.

Functional Table

Inputs

T/R H L

Outputs

Bus An Data to Bus Bn Bus Bn Data to Bus An

Bn Output Data Enabled An Output Data Enabled

Logic Diagram

GTLP2T152

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Voltage VI DC Output Voltage VO

Outputs 3-STATE

Outputs Active Note 2

DC Output Sink Current into A Port IOL

DC Output Source Current from

A Port IOH DC Output Sink Current into

B Port in the LOW State, IOL DC Input Diode Current IIK

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Datasheet ID: GTLP2T152M 633860