GTLP1B151M

GTLP1B151M Datasheet

GTLP1B151 1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path

Part	Datasheet
GTLP1B151M	GTLP1B151M (pdf)

Related Parts	Information
GTLP1B151MX	GTLP1B151MX
GTLP1B151K8X	GTLP1B151K8X

PDF Datasheet Preview
GTLP1B151 1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path GTLP1B151 1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path The GTLP1B151 is a 1-bit transceiver that provides LVTTL-to-GTLP signal level translation. Individual LVTTL and GTLP driver enables are also available. The GTLP1B151 offers separate LVTTL inputs and outputs, and can provide a feedback path for control and diagnostics monitoring. High-speed backplane operation is a direct result of GTLP’s reduced output swing <1V , reduced input threshold levels and output edge rate control. The edge rate control minimizes bus-settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor Logic GTL JEDEC standard JESD8-3. Fairchild’s GTLP has internal edge-rate control and is process, voltage and temperature compensated. GTLP’s I/O structure is similar to GTL and BTL but offers different output levels and receiver threshold. Typical GTLP output voltage levels are VOL = 0.5V, VOH = 1.5V, and VREF = 1V. s Separate LVTTL inputs and outputs s A feedback path for control and diagnostics monitoring s Bidirectional interface between GTLP and LVTTL logic levels s Designed with edge rate control circuitry to reduce out- put noise on the GTLP port s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Special PVT compensation circuitry to provide consis- tent performance over variations of process, supply voltage and temperature s TTL compatible driver and control inputs s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s A Port source/sink −24mA / +24mA s B Port sink +50mA Ordering Code: Order Number GTLP1B151M GTLP1B151MX GTLP1B151K8X Package Number Package Description M08A 8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow [TUBE] M08A 8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow [TAPE and REEL] MAB08A 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide Preliminary [TAPE and REEL] 2002 Fairchild Semiconductor Corporation DS500484 GTLP1B151 Pin Descriptions Connection Diagrams Pin Names OEB, OEC LVTTL Individual Output Enable Controls OEC is Active LOW VCC, GND, VREF Device Supplies A Port LVTTL Input B Port GTLP Input/Output C Port LVTTL Output US8 SOIC Functional Description The GTLP1B151 is a 1-bit transceiver that supports GTLP and LVTTL signal levels. Data polarity is non-inverting with separate LVTTL inputs and outputs and there are individual GTLP and LVTTL output enable controls. Functional Tables OEB H L Inputs Bn Output L H L H Outputs B Bus Enabled, C Bus Enabled B Bus Enabled, C Bus Enabled B Bus Enabled, C Bus Disabled B Bus Enabled, C Bus Disabled B Bus Disabled, C Bus Disabled B Bus Disabled, C Bus Disabled B Bus Disabled, C Bus Enabled B Bus Disabled, C Bus Enabled Logic Diagram GTLP1B151 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Voltage VI DC Output Voltage VO Outputs 3-STATE Outputs Active Note 2 DC Output Sink Current into C Port IOL DC Output Source Current from

PDF Datasheet Preview

GTLP1B151 1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path

GTLP1B151 1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path

The GTLP1B151 is a 1-bit transceiver that provides LVTTL-to-GTLP signal level translation. Individual LVTTL and GTLP driver enables are also available. The GTLP1B151 offers separate LVTTL inputs and outputs, and can provide a feedback path for control and diagnostics monitoring.

High-speed backplane operation is a direct result of GTLP’s reduced output swing <1V , reduced input threshold levels and output edge rate control. The edge rate control minimizes bus-settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor Logic GTL JEDEC standard JESD8-3.

Fairchild’s GTLP has internal edge-rate control and is process, voltage and temperature compensated. GTLP’s I/O structure is similar to GTL and BTL but offers different output levels and receiver threshold. Typical GTLP output voltage levels are VOL = 0.5V, VOH = 1.5V, and VREF = 1V.
s Separate LVTTL inputs and outputs s A feedback path for control and diagnostics monitoring s Bidirectional interface between GTLP and LVTTL logic
levels s Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port s VREF pin provides external supply reference voltage for
receiver threshold adjustibility s Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply voltage and temperature s TTL compatible driver and control inputs s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s A Port source/sink −24mA / +24mA s B Port sink +50mA
Ordering Code:

Order Number GTLP1B151M

GTLP1B151MX

GTLP1B151K8X

Package Number

Package Description

M08A
8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow [TUBE]

M08A
8-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow [TAPE and REEL]

MAB08A
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide

Preliminary [TAPE and REEL]
2002 Fairchild Semiconductor Corporation DS500484

GTLP1B151

Pin Descriptions

Connection Diagrams

Pin Names

OEB, OEC LVTTL Individual Output Enable Controls OEC is Active LOW

VCC, GND, VREF Device Supplies

A Port LVTTL Input

B Port GTLP Input/Output

C Port LVTTL Output

US8 SOIC

Functional Description

The GTLP1B151 is a 1-bit transceiver that supports GTLP and LVTTL signal levels. Data polarity is non-inverting with separate LVTTL inputs and outputs and there are individual GTLP and LVTTL output enable controls.

Functional Tables

OEB H L

Inputs

Bn Output

L H L H

Outputs

B Bus Enabled, C Bus Enabled B Bus Enabled, C Bus Enabled B Bus Enabled, C Bus Disabled B Bus Enabled, C Bus Disabled B Bus Disabled, C Bus Disabled B Bus Disabled, C Bus Disabled B Bus Disabled, C Bus Enabled B Bus Disabled, C Bus Enabled

Logic Diagram

GTLP1B151

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Voltage VI DC Output Voltage VO

Outputs 3-STATE

Outputs Active Note 2

DC Output Sink Current into C Port IOL

DC Output Source Current from

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Datasheet ID: GTLP1B151M 633859