GTLP16T1655MTD
GTLP16T1655MTD Datasheet
GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver with High Drive GTLP and Individual Byte Controls
| Part | Datasheet |
|---|---|
GTLP16T1655MTD |
GTLP16T1655MTD (pdf) |
| Related Parts | Information |
|---|---|
|
GTLP16T1655MTDX |
GTLP16T1655MTDX |
| PDF Datasheet Preview |
|---|
| GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver with High Drive GTLP and Individual Byte Controls GTLP16T1655 16-Bit LVTTL/GTLP Universal Bus Transceiver with High Drive GTLP and Individual Byte Controls The GTLP16T1655 is a 16-bit universal bus transceiver that provides LVTTL to GTLP signal level translation. It allows for transparent, latched and clocked modes of data transfer. The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing <1V , reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver Logic GTL JEDEC standard JESD8-3. Fairchild’s GTLP has internal edge-rate control and is process, voltage, and temperature PVT compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V. s Bidirectional interface between GTLP and LVTTL logic levels s Variable edge rate control pin to select desired edge rate on the GTLP backplane VERC s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature s TTL compatible driver and control inputs s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s D-type flip-flop, latch and transparent data paths s A Port source/sink −24mA/+24mA s B Port sink +100mA s Partitioned as two 8-bit transceivers with individual latch timing and output control but with a common clock s External pin to pre-condition I/O capacitance to high state VCCBIAS Ordering Code: Order Number Package Number Package Description GTLP16T1655MTD MTD64 64-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2005 Fairchild Semiconductor Corporation DS500172 GTLP16T1655 Connection Diagram Truth Tables Note 1 OEAB H L Inputs LEAB CLK X H L Pin Descriptions Pin Names 1OEAB 2OEAB A-to-B Output Enable Active LOW Byte 1 and Byte 2 1OEBA 2OEBA B-to-A Output Enable Active LOW Byte 1 and Byte 2 OE 1LEAB 2LEAB 1LEBA 2LEBA VREF CLK 1A1-1A8 2A1-2A8 1B1-1B8 2B1-2B8 Disables all I/O ports simultaneously A-to-B Latch Enable Transparent HIGH Byte 1 and Byte 2 B-to-A Latch Enable Transparent HIGH Byte 1 and Byte 2 GTLP Reference Voltage A-to-B and B-to-A Clock A Port I/O Byte 1 and Byte 2 B Port I/O Byte 1 and Byte 2 Output Mode High Impedance Transparent Transparent Registered Registered B0 Note 2 Previous State B0 Note 3 Previous State Inputs Outputs OEAB OEBA A Port B Port Note 4 Note 4 Active Active Active Active Inputs Output Edge |
| More datasheets: MIKROE-2523 | 02181600-120 | MM82C19N | PM2002-300 | PM2001-200 | PM2003-600 | PM2001-200-RC | PM2002-300-RC | APTGF50TA120PG | GTLP16T1655MTDX |
Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived GTLP16T1655MTD Datasheet file may be downloaded here without warranties.