GTLP10B320MTD

GTLP10B320MTD Datasheet

GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path

Part	Datasheet
GTLP10B320MTD	GTLP10B320MTD (pdf)

Related Parts	Information
GTLP10B320MTDX	GTLP10B320MTDX

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GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path The GTLP10B320 is a 10-bit Universal bus driver and receiver, with separate LVTTL inputs and outputs and a feedback path for diagnostics, that provides LVTTL to GTLP signal level translation. High speed backplane operation is a direct result of GTLP’s reduced output swing <1V , reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic GTL JEDEC standard JESD8-3. Fairchild’s GTLP has internal edge-rate control and is process, voltage and temperature PVT compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output low level is typically less than 0.5V, the output level high is 1.5V and the receiver threshold is 1.0V. s Bidirectional interface between GTLP and LVTTL logic levels s Variable edge rate control pin to select desired edge rate on GTLP port VERC s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Split LVTTL inputs and outputs s Special PVT compensation circuitry to provide consis- tent performance over variations of process, supply voltage and temperature s A feedback path for control and diagnostics monitoring s TTL compatible driver and control inputs s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s A Port source/sink −24mA/+24mA s B Port sink +50mA Ordering Code: Order Number Package Number Package Description GTLP10B320MTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Device is also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2001 Fairchild Semiconductor Corporation DS500483 GTLP10B320 Pin Descriptions Pin Names OEB, OEC B Port, C Port Output Enable respectively Active LOW VCC, GND, VREF Device Supplies LECLKAB, LECLKBC A-to-B, B-to-C Latch CLK respectively Transparent Active HIGH SEL SAB, SBC B0-B9 A0-A9 C0-C9 VERC Selects Internal Feedback Path Selects Register or Latch/Transparent Path for A-to-B and B-to-C respectively B Port GTLP I/O A Port LVTTL Inputs C Port LVTTL Outputs Edge Rate Control Pin GND = Slow Edge Rate VCC = Fast Edge Rate Connection Diagram Functional Description The GTLP10B320 is a 10-bit Universal driver and receiver containing D-Type flip-flop, latch, and transparent modes of operation for the data paths. In addition there is an internal feedback path that can be used for diagnostic monitoring or caching schemes. Data flow in each direction is controlled by the clock signals LECLKAB and LECLKBC and output enables OEB and OEC . The internal feedback path is controlled by the SEL pin and allows data transfer from Port A to Port C without requiring data to be output to the backplane. The internal feedback path is selected with SEL LOW and the B Port pin is selected with SEL HIGH. The data paths can also be configured for latch/transparent or register mode for each direction with the SAB and SBC pins. Data polarity is non-inverting with the GTLP outputs enabled via the OEB pin and the LVTTL outputs being enabled via the OEC pin. For A-to-B data flow the device is configured into a latch/ transparent or register mode by pin SAB. If SAB is LOW then the register mode is selected and the device operates on the LOW-to-HIGH transition of LECLKAB. If SAB is HIGH then the latch/transparent configuration is selected and a HIGH-to-LOW transition of LECLKAB stores data in the latch. If LECLKAB is HIGH the device is in transparent mode. When OEB is LOW the outputs are active and when OEB is HIGH the outputs are high impedance. GTLP10B320 Functional Tables I/O Path SEL = 1 External Feedback Path Note 2 Inputs OEB OEC SAB SBC LECLKAB LECLKBC Mode Register Register Register Register Latch Buffer Latch Buffer High Impedance X Note 1 Output level before the indicated steady state input conditions were established. Note 2 The data flow of B-to-C is similar except that OEC, SBC and LECLKBC are used. Outputs

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GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path

GTLP10B320 10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path

The GTLP10B320 is a 10-bit Universal bus driver and receiver, with separate LVTTL inputs and outputs and a feedback path for diagnostics, that provides LVTTL to GTLP signal level translation. High speed backplane operation is a direct result of GTLP’s reduced output swing <1V , reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic GTL JEDEC standard JESD8-3.

Fairchild’s GTLP has internal edge-rate control and is process, voltage and temperature PVT compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output low level is typically less than 0.5V, the output level high is 1.5V and the receiver threshold is 1.0V.
s Bidirectional interface between GTLP and LVTTL logic levels
s Variable edge rate control pin to select desired edge rate on GTLP port VERC
s VREF pin provides external supply reference voltage for receiver threshold adjustibility
s Split LVTTL inputs and outputs s Special PVT compensation circuitry to provide consis-
tent performance over variations of process, supply voltage and temperature s A feedback path for control and diagnostics monitoring s TTL compatible driver and control inputs s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s A Port source/sink −24mA/+24mA s B Port sink +50mA
Ordering Code:

Order Number Package Number

Package Description

GTLP10B320MTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Device is also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2001 Fairchild Semiconductor Corporation DS500483

GTLP10B320

Pin Descriptions

Pin Names

OEB, OEC

B Port, C Port Output Enable respectively Active LOW

VCC, GND, VREF Device Supplies

LECLKAB, LECLKBC

A-to-B, B-to-C Latch CLK respectively Transparent Active HIGH

SEL SAB, SBC

B0-B9 A0-A9 C0-C9 VERC

Selects Internal Feedback Path

Selects Register or Latch/Transparent Path for A-to-B and B-to-C respectively

B Port GTLP I/O

A Port LVTTL Inputs

C Port LVTTL Outputs

Edge Rate Control Pin GND = Slow Edge Rate VCC = Fast Edge Rate

Connection Diagram

Functional Description

The GTLP10B320 is a 10-bit Universal driver and receiver containing D-Type flip-flop, latch, and transparent modes of operation for the data paths. In addition there is an internal feedback path that can be used for diagnostic monitoring or caching schemes. Data flow in each direction is controlled by the clock signals LECLKAB and LECLKBC and output enables OEB and OEC . The internal feedback path is controlled by the SEL pin and allows data transfer from Port A to Port C without requiring data to be output to the backplane. The internal feedback path is selected with SEL LOW and the B Port pin is selected with SEL HIGH. The data paths can also be configured for latch/transparent or register mode for each direction with the SAB and SBC
pins. Data polarity is non-inverting with the GTLP outputs enabled via the OEB pin and the LVTTL outputs being enabled via the OEC pin.

For A-to-B data flow the device is configured into a latch/ transparent or register mode by pin SAB. If SAB is LOW then the register mode is selected and the device operates on the LOW-to-HIGH transition of LECLKAB. If SAB is HIGH then the latch/transparent configuration is selected and a HIGH-to-LOW transition of LECLKAB stores data in the latch. If LECLKAB is HIGH the device is in transparent mode. When OEB is LOW the outputs are active and when OEB is HIGH the outputs are high impedance.

GTLP10B320

Functional Tables

I/O Path SEL = 1 External Feedback Path Note 2

Inputs

OEB OEC SAB SBC LECLKAB LECLKBC

Mode

Register

Register

Register

Register

Latch

Buffer

Latch

Buffer

High Impedance X

Note 1 Output level before the indicated steady state input conditions were established.

Note 2 The data flow of B-to-C is similar except that OEC, SBC and LECLKBC are used.

Outputs

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Datasheet ID: GTLP10B320MTD 633855