ADP3198AJCPZ-RL

ADP3198AJCPZ-RL Datasheet

ADP3198A

Part	Datasheet
ADP3198AJCPZ-RL	ADP3198AJCPZ-RL (pdf)

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8-Bit Programmable 2- to 4-Phase Synchronous Buck Controller ADP3198A Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per phase mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Fast enhanced PWM FEPWM flex mode for excellent load transient performance Active current balancing between all output phases Built-in power-good/crowbar blanking supports on-the-fly VID code changes Digitally programmable V to V output supports both VR10.x and VR11 specifications Programmable short-circuit protection with programmable latch-off delay Desktop PC power supplies for next generation processors VRM modules The ADP3198A1 is a highly efficient, multiphase, synchronous buck-switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. It uses an internal 8-bit DAC to read a voltage identification VID code directly from the processor, which is used to set the output voltage between V and V. This device uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck-switching stages. FUNCTIONAL BLOCK DIAGRAM VCC 31 RT RAMPADJ GND 18 SHUNT REGULATOR UVLO SHUTDOWN 850mV + 150mV + CSREF + DAC 350mV PWRGD 2 DELAY OSCILLATOR 19 OD CURRENT BALANCING CIRCUIT + CMP + CMP + CMP + CMP SET EN RESET 30 PWM1 RESET 29 PWM2 RESET 28 PWM3 2/3/4-PHASE DRIVER LOGIC 27 PWM4 RESET CROWBAR CURRENT LIMIT Power-Good 14 Output Crowbar 14 Output Enable and UVLO 14 Thermal Monitoring 14 Application 19 Setting the Clock 19 Soft Start Delay 19 Current-Limit Latch-Off Delay Times 19 Inductor Selection 19 Current Sense 20 Inductor DCR Temperature Correction 21 Output Offset 22 COUT Selection 22 Power 23 Ramp Resistor 24 COMP Pin Ramp 25 Current-Limit 25 Feedback Loop Compensation 25 CIN Selection and Input Current di/dt Reduction.................. 27 Thermal Monitor Design 27 Shunt Resistor 28 Tuning the ADP3198A 28 Layout and Component Placement 30 Outline Dimensions 31 Ordering Guide 31 ADP3198A SPECIFICATIONS VCC = 5 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1 Table Parameter REFERENCE CURRENT Reference Bias Voltage Reference Bias Current ERROR AMPLIFIER Output Voltage Range2 Accuracy Load Line Positioning Accuracy Differential Nonlinearity Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate LLSET Input Voltage Range LLSET Input Bias Current Boot Voltage Hold Time VID INPUTS Input Low Voltage Input High Voltage Input Current VID Transition Delay Time2 No CPU Detection Turn-Off Delay Time2 OSCILLATOR Frequency Range2 Frequency Variation Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Output Voltage Range Output Current Limit Latch-Off Delay Time IMON Output CURRENT BALANCE AMPLIFIER Common-Mode Range Input Resistance Input Current Input Current Matching CURRENT-LIMIT COMPARATOR ILIMIT Bias Current Symbol Conditions VIREF IIREF RIREF = 100 kΩ VCOMP VFB VFB BOOT Relative to nominal DAC output, referenced to FBRTN, LLSET = CSREF see Figure 2 In startup CSREF − LLSET = 80 mV IFB IFBRTN ICOMP GBW ERR VLLSET ILLSET tBOOT IFB = IIREF FB forced to VOUT 3% COMP = FB COMP = FB Relative to CSREF CDELAY = 10 nF VIL VID VIH VID IIN VID VID X , VIDSEL VID X , VIDSEL VID code change to FB change VID code change to PWM going low fOSC fPHASE VRT VRAMPADJ IRAMPADJ TA = 25°C, RT = 205 kΩ, 4-phase TA = 25°C, RT = 118 kΩ, 4-phase TA = 25°C, RT = 55 kΩ, 4-phase RT = 205 kΩ to GND RAMPADJ − FB VOS CSA IBIAS CSSUM GBW CSA CSSUM − CSREF see Figure 3 CSSUM = CSCOMP CCSCOMP = 10 pF CSSUM and CSREF ICSCOMP tOC DELAY IMON CDELAY = 10 nF 10 x CSREF − CSCOMP > 50 mV VSW X CM RSW X ISW X SW X = 0 V SW X = 0 V SW X = 0 V IILIMIT IILIMIT = 2/3 x IIREF Min Typ −78 −80 −1 15 65 500 20 25 −250 −10 2 −1 400 5 180 200 400 800 −50 1 ORDERING GUIDE Model Temperature Range ADP3198AJCPZ-RL1 0°C to 85°C Package Description 40-Lead Frame Chip Scale Package [LFCSP_VQ] 1 Z = RoHS Compliant Part. Package Option Ordering Quantity CP-40-1 2,500 ADP3198A NOTES 2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06787-0-5/07 0

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8-Bit Programmable 2- to 4-Phase Synchronous Buck Controller

ADP3198A

Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per phase
mV worst-case differential sensing error over temperature

Logic-level PWM outputs for interface to external high power drivers

Fast enhanced PWM FEPWM flex mode for excellent load transient performance

Active current balancing between all output phases Built-in power-good/crowbar blanking supports on-the-fly

VID code changes Digitally programmable V to V output supports both

VR10.x and VR11 specifications Programmable short-circuit protection with programmable
latch-off delay

Desktop PC power supplies for next generation processors VRM modules

The ADP3198A1 is a highly efficient, multiphase, synchronous buck-switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. It uses an internal 8-bit DAC to read a voltage identification VID code directly from the processor, which is used to set the output voltage between V and V. This device uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck-switching stages.

FUNCTIONAL BLOCK DIAGRAM

VCC 31

RT RAMPADJ

GND 18

SHUNT REGULATOR

UVLO SHUTDOWN
850mV
+ 150mV
+ CSREF +

DAC 350mV

PWRGD 2

DELAY

OSCILLATOR
19 OD

CURRENT BALANCING CIRCUIT
+ CMP
+ CMP
+ CMP
+ CMP

SET EN RESET
30 PWM1

RESET
29 PWM2

RESET
28 PWM3
2/3/4-PHASE DRIVER LOGIC 27 PWM4

RESET

CROWBAR

CURRENT LIMIT
Power-Good 14 Output Crowbar 14 Output Enable and UVLO 14 Thermal Monitoring 14 Application 19 Setting the Clock 19 Soft Start Delay 19 Current-Limit Latch-Off Delay Times 19 Inductor Selection 19 Current Sense 20 Inductor DCR Temperature Correction 21 Output Offset 22 COUT Selection 22 Power 23 Ramp Resistor 24 COMP Pin Ramp 25 Current-Limit 25 Feedback Loop Compensation 25 CIN Selection and Input Current di/dt Reduction.................. 27 Thermal Monitor Design 27 Shunt Resistor 28 Tuning the ADP3198A 28 Layout and Component Placement 30 Outline Dimensions 31 Ordering Guide 31

ADP3198A

SPECIFICATIONS

VCC = 5 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1

Table Parameter REFERENCE CURRENT

Reference Bias Voltage Reference Bias Current ERROR AMPLIFIER Output Voltage Range2 Accuracy

Load Line Positioning Accuracy Differential Nonlinearity Input Bias Current FBRTN Current Output Current Gain Bandwidth Product Slew Rate LLSET Input Voltage Range LLSET Input Bias Current Boot Voltage Hold Time VID INPUTS Input Low Voltage Input High Voltage Input Current VID Transition Delay Time2 No CPU Detection Turn-Off Delay Time2 OSCILLATOR Frequency Range2 Frequency Variation

Output Voltage RAMPADJ Output Voltage RAMPADJ Input Current Range CURRENT SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range Output Voltage Range Output Current Limit Latch-Off Delay Time IMON Output CURRENT BALANCE AMPLIFIER Common-Mode Range Input Resistance Input Current Input Current Matching CURRENT-LIMIT COMPARATOR ILIMIT Bias Current

Symbol Conditions

VIREF IIREF

RIREF = 100 kΩ

VCOMP VFB

VFB BOOT

Relative to nominal DAC output, referenced to FBRTN, LLSET = CSREF see Figure 2 In startup CSREF − LLSET = 80 mV

IFB IFBRTN ICOMP GBW ERR

VLLSET ILLSET tBOOT

IFB = IIREF

FB forced to VOUT 3% COMP = FB COMP = FB Relative to CSREF

CDELAY = 10 nF

VIL VID VIH VID IIN VID

VID X , VIDSEL VID X , VIDSEL

VID code change to FB change VID code change to PWM going low
fOSC fPHASE

VRT VRAMPADJ IRAMPADJ

TA = 25°C, RT = 205 kΩ, 4-phase TA = 25°C, RT = 118 kΩ, 4-phase TA = 25°C, RT = 55 kΩ, 4-phase RT = 205 kΩ to GND RAMPADJ − FB

VOS CSA IBIAS CSSUM GBW CSA

CSSUM − CSREF see Figure 3

CSSUM = CSCOMP CCSCOMP = 10 pF CSSUM and CSREF

ICSCOMP tOC DELAY IMON

CDELAY = 10 nF 10 x CSREF − CSCOMP > 50 mV

VSW X CM RSW X ISW X

SW X = 0 V SW X = 0 V SW X = 0 V

IILIMIT

IILIMIT = 2/3 x IIREF

Min Typ
−78 −80 −1 15
65 500 20 25 −250 −10 2
−1
400 5
180 200
400 800 −50 1
ORDERING GUIDE

Model

Temperature Range

ADP3198AJCPZ-RL1 0°C to 85°C

Package Description 40-Lead Frame Chip Scale Package [LFCSP_VQ]
1 Z = RoHS Compliant Part.
Package Option Ordering Quantity

CP-40-1
2,500

ADP3198A NOTES
2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

D06787-0-5/07 0

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ADP3198AJCPZ-RL Datasheet file may be downloaded here without warranties.

Datasheet ID: ADP3198AJCPZ-RL 517861