CY14B101K-SP35XC

CY14B101K-SP35XC Datasheet

CY14B101K

Part	Datasheet
CY14B101K-SP35XC	CY14B101K-SP35XC (pdf)

Related Parts	Information
CY14B101K-SP25XI	CY14B101K-SP25XI
CY14B101K-SP35XI	CY14B101K-SP35XI
CY14B101K-SP35XCT	CY14B101K-SP35XCT
CY14B101K-SP35XIT	CY14B101K-SP35XIT
CY14B101K-SP45XCT	CY14B101K-SP45XCT
CY14B101K-SP45XI	CY14B101K-SP45XI
CY14B101K-SP45XIT	CY14B101K-SP45XIT
CY14B101K-SP45XC	CY14B101K-SP45XC
CY14B101K-SP25XC	CY14B101K-SP25XC

PDF Datasheet Preview
CY14B101K 1 Mbit 128K x 8 nvSRAM With Real Time Clock Endurance to 200K cycles Data retention 20 years at 55°C • 25 ns, 35 ns, and 45 ns access times • Single 3V operation with tolerance of +20%, • Pin compatible with STK17TA8 • Commercial and industrial temperature • Data integrity of Cypress nvSRAM combined with full featured Real Time Clock RTC Low power, 350 nA RTC current Capacitor or battery backup for RTC • Watchdog timer • Clock alarm with programmable interrupts • Hands off automatic STORE on power down with only a small capacitor • 48-Pin SSOP package ROHS compliant s Functional Description n The Cypress CY14B101K combines a 1 Mbit nonvolatile static ig RAM with a full featured real time clock in a monolithic integrated circuit. The embedded nonvolatile elements incorporate s QuantumTrap technology producing the world’s most reliable e nonvolatile memory. The SRAM is read and written an infinite D number of times, while independent, nonvolatile data resides in • STORE to QuantumTrap initiated by software, device pin, or on power down ew • RECALL to SRAM initiated by software or on power up N • Infinite READ, WRITE, and RECALL cycles r • High reliability the nonvolatile elements. The Real Time Clock function provides an accurate clock with leap year tracking and a programmable high accuracy oscillator. The alarm function is programmable for one time alarm or periodic seconds, minutes, hours, or days. There is also a programmable watchdog timer for process control. INPUT BUFFERS ROW DECODER ed fo Logic Block Diagram nd A5 e A6 A7 A8 A 12 A 13 m A14 o A16 ec DQ0 R DQ2 tDQ4 oDQ5 NDQ7 QuantumTrap 1024 x 1024 STORE STATIC RAM ARRAY 1024 X 1024 RECALL COLUMN IO COLUMN DEC A0 A1 A2 A3 A4 A10 A11 VCAP POWER CONTROL STORE/ RECALL CONTROL VRTCbat VRTCcap SOFTWARE DETECT Capacitance 17 Thermal Resistance 17 AC Test Conditions 17 AC Switching Characteristics 18 AC Switching Characteristics continued 19 AutoStore or Power Up RECALL 20 Software Controlled STORE/RECALL Cycles 21 Hardware STORE Cycle 22 Soft Sequence Commands 22 RTC Characteristics 23 Truth Table For SRAM Operations 23 Part Numbering Nomenclature 24 Ordering Information 25 Package Diagrams 26 Document History Page 27 Sales, Solutions, and Legal Information 29 Worldwide Sales and Design Support 29 Products 29 Page 2 of 29 [+] Feedback CY14B101K Pin Configurations Figure 48-Pin SSOP V CAP 48-SSOP Top View Not To Scale 43 42 41 40 39 38 37 36 35 A8 A9 s NC n A11 ig NC sNC eVSS DNC V RTCbat r DQ1 fo DQ2 V RTCcap de Table Pin Definitions en Pin Name Alt A0 A16 m DQ0 DQ7 ec CE ot X1 N X2 I/O Type Input Input Output No Connect Input Input Output Input Description Address Inputs. Used to select one of the 131,072 bytes of the nvSRAM. Bidirectional Data I/O Lines. Used as input or output lines depending on operation No Connects. This pin is not connected to the die Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active low OE input enables the data output buffers during READ cycles. Deasserting OE high causes the I/O pins to tri-state. Crystal Connection Drives crystal on start up. Crystal Connection for kHz crystal. VRTCcap Power Supply Capacitor Supplied Backup RTC Supply Voltage. Left unconnected if VRTCbat is used VRTCbat Power Supply Battery Supplied Backup RTC Supply Voltage. Left unconnected if VRTCcap is used Output Interrupt Output. Program to respond to the clock alarm, the watchdog timer, and the power monitor. Programmable to either active HIGH push or pull or LOW open drain . VSS VCC HSB Ground for the Device. Must be connected to ground of the system. Power Supply Power Supply Inputs to the Device. Input Output Hardware Store Busy. When LOW this output indicates a Hardware Store is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin HIGH if not connected connection optional . VCAP Ordering Information These parts are not recommended for new designs. Speed ns Ordering Code Package Diagram Package Type Operating Range CY14B101K-SP25XC 51-85061 48-pin SSOP Commercial CY14B101K-SP25XCT CY14B101K-SP25XI 51-85061 48-pin SSOP Industrial CY14B101K-SP25XIT CY14B101K-SP35XC CY14B101K-SP35XCT CY14B101K-SP35XI CY14B101K-SP35XIT CY14B101K-SP45XC CY14B101K-SP45XCT 51-85061 48-pin SSOP 51-85061 48-pin SSOP 51-85061 48-pin SSOP Commercial nsIndustrial Desig Commercial CY14B101K-SP45XI 51-85061 48-pin SSOP CY14B101K-SP45XIT Not Recommended for New All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts. Industrial Page 25 of 29 [+] Feedback Package Diagrams Figure 48-Pin Shrunk Small Outline Package 51-85061 CY14B101K Designs Not Recommended for New 51-85061-C Page 26 of 29 [+] Feedback CY14B101K Document History Page Document Title CY14B101K 1 Mbit 128K x 8 nvSRAM With Real Time Clock Document Number 001-06401 ECN NO. Orig. of Change Submission Date Description of Change 425138 TUP Updated Part Numbering Nomenclature and Ordering Infor- s mation e Added RTC Characteristics Table D Added RTC Recommended Component Configuration E F G *H 503272 PCI See ECN ed for New 597002 TUP See ECN mmend 688776 VKN See ECN eco 1349963 UHA/SFV See ECN ot R 1739984 vsutmp8/AESA N 2427986 GVCH/PYRS See ECN 04/23/08 Changed from Advance to Preliminary Changed the term “Unlimited” to “Infinite” Changed Endurance from 500K Cycles to 200K Cycles Added temperature spec. to Data Retention - 20 years at 55xC Removed Icc1 values from the DC table for 25 ns and 35 ns Industrial Grade Changed Icc2 value from 3 mA to 6 mA in the DC Table Added a footnote on VIH Added footnote 18 related to using the software command Changed VSWITCH min from 2.55V to 2.45V Updated Part Nomenclature Table and Ordering Information Table Removed VSWITCH min specification from the AutoStore/Power Up RECALL Table Changed tGLAX specification from 20 ns to 1 ns Added tDELAY max specification of 70 ms in the Hardware STORE Cycle Table Removed tHLBL specification Changed tSS specification form 70 ms min to 70 ms max Changed VCAP max from 57 mF to 120 mF Added footnote 7 related to HSB Added footnote 8 related to INT pin Changed tGLAX to tGHAX Removed ABE bit from interrupt register Changed from Preliminary to Final Added Note 5 regarding the W bit in the Flag register Updated Ordering Information Table Added Pinout diagram and Pin definition Table Move to external web Page 27 of 29 [+] Feedback CY14B101K Document Title CY14B101K 1 Mbit 128K x 8 nvSRAM With Real Time Clock Document Number 001-06401 ECN NO. Orig. of Change Submission Date Description of Change 2663934 GVCH/PYRS 02/24/09 Updated Features Updated pin definition of WE Removed AutoStore enable/disable section Added Best practices Updated “Reading the clock”, “Backup Power”, “Stopping and starting the Oscillator” and “Alarm” descriptions under RTC operation Modified “Figure RTC Recommended Component Configu- s ration” n Added footnotes 4, 5 and 6 ig Added default values to RTC Register Map” table Updated flag register description in Register Map Detail” table s Added Industrial specs for 25ns and 35ns speed e Changed VIH from Vcc+0.3 to Vcc+0.5 D Added “Data Retention and Endurance” table on page 15 Not Recommended for New 2815609 GVCH 11/26/09 Added Thermal resistance values Added alternate parameters in the AC switching characteristics table Renamed tOH to tOHA Changed tHRECALL from 20 to 40ms Changed tRECALL spec from 100us to 170us Including tss of 70us Renamed tAS to tSA Renamed tGHAX to tHA Updated Figure 13, 14, 15 and 16 Renamed tHLHX to tPHSB Added truth table for SRAM operations Added note in the Ordering Information table and watermark to state that the parts in this data sheet are not recommended for new designs. Added the Contents page. Page 28 of 29 [+] Feedback CY14B101K Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC psoc.cypress.com Clocks & Buffers clocks.cypress.com Wireless Memories Image Sensors wireless.cypress.com memory.cypress.com image.cypress.com Designs ot Recommended for New Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used N for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 29 of 29 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY14B101K
1 Mbit 128K x 8 nvSRAM With Real Time Clock

Endurance to 200K cycles Data retention 20 years at 55°C
• 25 ns, 35 ns, and 45 ns access times
• Single 3V operation with tolerance of +20%,
• Pin compatible with STK17TA8
• Commercial and industrial temperature
• Data integrity of Cypress nvSRAM combined with full featured Real Time Clock RTC Low power, 350 nA RTC current Capacitor or battery backup for RTC
• Watchdog timer
• Clock alarm with programmable interrupts
• Hands off automatic STORE on power down with only a small capacitor
• 48-Pin SSOP package ROHS compliant
s Functional Description n The Cypress CY14B101K combines a 1 Mbit nonvolatile static ig RAM with a full featured real time clock in a monolithic integrated
circuit. The embedded nonvolatile elements incorporate
s QuantumTrap technology producing the world’s most reliable e nonvolatile memory. The SRAM is read and written an infinite D number of times, while independent, nonvolatile data resides in
• STORE to QuantumTrap initiated by software, device pin, or on power down
ew
• RECALL to SRAM initiated by software or on power up N
• Infinite READ, WRITE, and RECALL cycles r
• High reliability
the nonvolatile elements.

The Real Time Clock function provides an accurate clock with leap year tracking and a programmable high accuracy oscillator. The alarm function is programmable for one time alarm or periodic seconds, minutes, hours, or days. There is also a programmable watchdog timer for process control.

INPUT BUFFERS

ROW DECODER
ed fo Logic Block Diagram nd A5 e A6

A7 A8

A 12 A 13
m A14
o A16 ec DQ0

R DQ2
tDQ4 oDQ5

NDQ7

QuantumTrap 1024 x 1024

STORE

STATIC RAM ARRAY
1024 X 1024

RECALL

COLUMN IO COLUMN DEC

A0 A1 A2 A3 A4 A10 A11

VCAP

POWER CONTROL

STORE/ RECALL CONTROL

VRTCbat VRTCcap

SOFTWARE DETECT
Capacitance 17 Thermal Resistance 17 AC Test Conditions 17 AC Switching Characteristics 18 AC Switching Characteristics continued 19 AutoStore or Power Up RECALL 20 Software Controlled STORE/RECALL Cycles 21 Hardware STORE Cycle 22 Soft Sequence Commands 22 RTC Characteristics 23 Truth Table For SRAM Operations 23 Part Numbering Nomenclature 24 Ordering Information 25 Package Diagrams 26 Document History Page 27 Sales, Solutions, and Legal Information 29

Worldwide Sales and Design Support 29 Products 29

Page 2 of 29 [+] Feedback

CY14B101K

Pin Configurations

Figure 48-Pin SSOP

V CAP
48-SSOP

Top View

Not To Scale
43 42 41 40 39 38 37 36 35

A8 A9
s NC n A11 ig NC
sNC eVSS DNC

V RTCbat
r DQ1
fo DQ2

V RTCcap
de Table Pin Definitions
en Pin Name Alt

A0 A16
m DQ0 DQ7
ec CE
ot X1 N X2

I/O Type Input

Input Output No Connect

Input

Input

Output Input

Description Address Inputs. Used to select one of the 131,072 bytes of the nvSRAM. Bidirectional Data I/O Lines. Used as input or output lines depending on operation No Connects. This pin is not connected to the die Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active low OE input enables the data output buffers during READ cycles. Deasserting OE high causes the I/O pins to tri-state. Crystal Connection Drives crystal on start up. Crystal Connection for kHz crystal.

VRTCcap

Power Supply Capacitor Supplied Backup RTC Supply Voltage. Left unconnected if VRTCbat is used

VRTCbat

Power Supply Battery Supplied Backup RTC Supply Voltage. Left unconnected if VRTCcap is used

Output Interrupt Output. Program to respond to the clock alarm, the watchdog timer, and the power
monitor. Programmable to either active HIGH push or pull or LOW open drain .

VSS VCC HSB

Ground for the Device. Must be connected to ground of the system.

Power Supply Power Supply Inputs to the Device.

Input Output Hardware Store Busy. When LOW this output indicates a Hardware Store is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin HIGH if not connected connection optional .

VCAP
Ordering Information

These parts are not recommended for new designs.

Speed ns
Ordering Code

Package Diagram

Package Type

Operating Range

CY14B101K-SP25XC
51-85061 48-pin SSOP

Commercial

CY14B101K-SP25XCT

CY14B101K-SP25XI
51-85061 48-pin SSOP

Industrial

CY14B101K-SP25XIT

CY14B101K-SP35XC

CY14B101K-SP35XCT

CY14B101K-SP35XI

CY14B101K-SP35XIT

CY14B101K-SP45XC

CY14B101K-SP45XCT
51-85061 48-pin SSOP 51-85061 48-pin SSOP 51-85061 48-pin SSOP

Commercial
nsIndustrial Desig Commercial

CY14B101K-SP45XI
51-85061 48-pin SSOP

CY14B101K-SP45XIT

Not Recommended for New All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts.

Industrial

Page 25 of 29 [+] Feedback

Package Diagrams

Figure 48-Pin Shrunk Small Outline Package 51-85061

CY14B101K

Designs

Not Recommended for New
51-85061-*C

Page 26 of 29 [+] Feedback

CY14B101K

Document History Page

Document Title CY14B101K 1 Mbit 128K x 8 nvSRAM With Real Time Clock Document Number 001-06401

ECN NO. Orig. of Change

Submission Date

Description of Change
425138 TUP
Updated Part Numbering Nomenclature and Ordering Infor-
s mation e Added RTC Characteristics Table D Added RTC Recommended Component Configuration
*E *F *G *H
503272 PCI

See ECN
ed for New 597002 TUP

See ECN
mmend 688776 VKN

See ECN
eco 1349963 UHA/SFV

See ECN
ot R 1739984 vsutmp8/AESA N 2427986 GVCH/PYRS

See ECN 04/23/08
Changed from Advance to Preliminary Changed the term “Unlimited” to “Infinite” Changed Endurance from 500K Cycles to 200K Cycles Added temperature spec. to Data Retention - 20 years at 55xC Removed Icc1 values from the DC table for 25 ns and 35 ns Industrial Grade Changed Icc2 value from 3 mA to 6 mA in the DC Table Added a footnote on VIH Added footnote 18 related to using the software command Changed VSWITCH min from 2.55V to 2.45V Updated Part Nomenclature Table and Ordering Information Table

Removed VSWITCH min specification from the AutoStore/Power Up RECALL Table Changed tGLAX specification from 20 ns to 1 ns Added tDELAY max specification of 70 ms in the Hardware STORE Cycle Table Removed tHLBL specification Changed tSS specification form 70 ms min to 70 ms max Changed VCAP max from 57 mF to 120 mF

Added footnote 7 related to HSB Added footnote 8 related to INT pin Changed tGLAX to tGHAX Removed ABE bit from interrupt register
Changed from Preliminary to Final Added Note 5 regarding the W bit in the Flag register Updated Ordering Information Table

Added Pinout diagram and Pin definition Table

Move to external web

Page 27 of 29 [+] Feedback

CY14B101K

Document Title CY14B101K 1 Mbit 128K x 8 nvSRAM With Real Time Clock Document Number 001-06401

ECN NO. Orig. of Change

Submission Date

Description of Change
2663934

GVCH/PYRS
02/24/09

Updated Features

Updated pin definition of WE

Removed AutoStore enable/disable section

Added Best practices

Updated “Reading the clock”, “Backup Power”, “Stopping and
starting the Oscillator” and “Alarm” descriptions under RTC
operation Modified “Figure RTC Recommended Component Configu-
s ration” n Added footnotes 4, 5 and 6 ig Added default values to RTC Register Map” table

Updated flag register description in Register Map Detail” table
s Added Industrial specs for 25ns and 35ns speed e Changed VIH from Vcc+0.3 to Vcc+0.5 D Added “Data Retention and Endurance” table on page 15

Not Recommended for New 2815609

GVCH
11/26/09

Added Thermal resistance values Added alternate parameters in the AC switching characteristics table Renamed tOH to tOHA Changed tHRECALL from 20 to 40ms Changed tRECALL spec from 100us to 170us Including tss of 70us Renamed tAS to tSA Renamed tGHAX to tHA Updated Figure 13, 14, 15 and 16 Renamed tHLHX to tPHSB Added truth table for SRAM operations
Added note in the Ordering Information table and watermark to state that the parts in this data sheet are not recommended for new designs. Added the Contents page.

Page 28 of 29 [+] Feedback

CY14B101K

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products

PSoC
psoc.cypress.com

Clocks & Buffers
clocks.cypress.com

Wireless Memories Image Sensors
wireless.cypress.com memory.cypress.com
image.cypress.com

Designs
ot Recommended for New Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used

N for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 29 of 29

AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.
[+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY14B101K-SP35XC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY14B101K-SP35XC 507655