ADP3192JCPZ-RL

ADP3192JCPZ-RL Datasheet

8-Bit Programmable 2- to 4-Phase Synchronous Buck Controller ADP3192

Part	Datasheet
ADP3192JCPZ-RL	ADP3192JCPZ-RL (pdf)

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8-Bit Programmable 2- to 4-Phase Synchronous Buck Controller ADP3192 Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per phase mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high power drivers Enhanced PWM flex mode for excellent load transient performance Active current balancing between all output phases Built-in power-good/crowbar blanking supports on-the-fly VID code changes Digitally programmable V to V output supports both VR10.x and VR11 specifications Programmable short-circuit protection with programmable latch-off delay Desktop PC power supplies for Next generation processors VRM modules The ADP31921 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. It uses an internal 8-bit DAC to read a voltage identification VID code directly from the processor, which is used to set the output voltage between V and V. This device uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck switching stages. The ADP3192 also includes programmable no load offset and slope functions to adjust the output voltage as a function of the load current, optimally positioning it for a system transient. The ADP3192 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed powergood output that accommodates on-the-fly output voltage changes requested by the CPU. FUNCTIONAL BLOCK DIAGRAM VCC 31 RT RAMPADJ GND 18 SHUNT REGULATOR UVLO SHUTDOWN 850mV + 150mV + CSREF + DAC 350mV PWRGD 2 DELAY OSCILLATOR 19 OD CURRENT BALANCING CIRCUIT + CMP + CMP + CMP + CMP SET EN RESET 30 PWM1 RESET 29 PWM2 RESET 28 PWM3 2/3/4-PHASE DRIVER LOGIC 27 PWM4 RESET CROWBAR Power-Good 14 Output Crowbar 14 Output Enable and UVLO 14 Thermal Monitoring 14 Application 20 Setting the Clock 20 Soft Start Delay 20 Current-Limit Latch-Off Delay Times 20 Inductor Selection 21 Current Sense 22 Inductor DCR Temperature Correction 22 Output Offset 24 COUT Selection 24 Power 25 Ramp Resistor 26 COMP Pin Ramp 26 Current-Limit 26 Feedback Loop Compensation 27 CIN Selection and Input Current di/dt Reduction.................. 28 Thermal Monitor Design 28 Shunt Resistor 29 Tuning the ADP3192 29 Layout and Component Placement 31 Outline Dimensions 32 Ordering Guide 32 ADP3192 SPECIFICATIONS VCC = 5 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1 Table Parameter Symbol Conditions Min Typ REFERENCE CURRENT Reference Bias Voltage VIREF Reference Bias Current IIREF RIREF = 100 kΩ ERROR AMPLIFIER Output Voltage Range2 Accuracy VCOMP VFB Relative to nominal DAC output, referenced to FBRTN, LLSET = CSREF see Figure 2 Load Line Positioning Accuracy VFB BOOT In startup CSREF − LLSET = 80 mV −78 −80 Differential Nonlinearity −1 Input Bias Current IFB = IIREF FBRTN Current IFBRTN Output Current ICOMP FB forced to VOUT 3% Gain Bandwidth Product GBW ERR COMP = FB Slew Rate COMP = FB LLSET Input Voltage Range LLSET Input Bias Current BOOT Voltage Hold Time VLLSET ILLSET tBOOT Relative to CSREF CDELAY = 10 nF −250 −10 VID INPUTS Input Low Voltage VIL VID ORDERING GUIDE Model Temperature Range ADP3192JCPZ-RL1 0°C to 85°C 1 Z = Pb-free part. Package Description Package Option Ordering Quantity 40-Lead Frame Chip Scale Package [LFCSP_VQ] CP-40 2,500 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06093-0-6/06 0

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8-Bit Programmable 2- to 4-Phase Synchronous Buck Controller ADP3192

Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per phase
mV worst-case differential sensing error over temperature

Logic-level PWM outputs for interface to external high power drivers

Enhanced PWM flex mode for excellent load transient performance

Active current balancing between all output phases Built-in power-good/crowbar blanking supports on-the-fly

VID code changes Digitally programmable V to V output supports both

VR10.x and VR11 specifications Programmable short-circuit protection with programmable
latch-off delay

Desktop PC power supplies for Next generation processors VRM modules

The ADP31921 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. It uses an internal 8-bit DAC to read a voltage identification VID code directly from the processor, which is used to set the output voltage between V and V.

This device uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, or 4-phase operation, allowing for the construction of up to four complementary buck switching stages.

The ADP3192 also includes programmable no load offset and slope functions to adjust the output voltage as a function of the load current, optimally positioning it for a system transient. The ADP3192 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed powergood output that accommodates on-the-fly output voltage changes requested by the CPU.

FUNCTIONAL BLOCK DIAGRAM

VCC 31

RT RAMPADJ

GND 18

SHUNT REGULATOR

UVLO SHUTDOWN
850mV
+ 150mV
+ CSREF +

DAC 350mV

PWRGD 2

DELAY

OSCILLATOR
19 OD

CURRENT BALANCING CIRCUIT
+ CMP
+ CMP
+ CMP
+ CMP

SET EN RESET
30 PWM1

RESET
29 PWM2

RESET
28 PWM3
2/3/4-PHASE DRIVER LOGIC 27 PWM4

RESET

CROWBAR
Power-Good 14 Output Crowbar 14 Output Enable and UVLO 14 Thermal Monitoring 14 Application 20 Setting the Clock 20 Soft Start Delay 20 Current-Limit Latch-Off Delay Times 20 Inductor Selection 21 Current Sense 22 Inductor DCR Temperature Correction 22 Output Offset 24 COUT Selection 24 Power 25 Ramp Resistor 26 COMP Pin Ramp 26 Current-Limit 26 Feedback Loop Compensation 27 CIN Selection and Input Current di/dt Reduction.................. 28 Thermal Monitor Design 28 Shunt Resistor 29 Tuning the ADP3192 29 Layout and Component Placement 31 Outline Dimensions 32 Ordering Guide 32

ADP3192

SPECIFICATIONS

VCC = 5 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1 Table

Parameter

Symbol Conditions

Min Typ

REFERENCE CURRENT

Reference Bias Voltage

VIREF

Reference Bias Current

IIREF

RIREF = 100 kΩ

ERROR AMPLIFIER

Output Voltage Range2 Accuracy

VCOMP VFB

Relative to nominal DAC output, referenced to FBRTN, LLSET = CSREF see Figure 2

Load Line Positioning Accuracy

VFB BOOT

In startup CSREF − LLSET = 80 mV
−78 −80

Differential Nonlinearity
−1

Input Bias Current

IFB = IIREF

FBRTN Current

IFBRTN

Output Current

ICOMP

FB forced to VOUT 3%

Gain Bandwidth Product

GBW ERR COMP = FB

Slew Rate

COMP = FB

LLSET Input Voltage Range LLSET Input Bias Current BOOT Voltage Hold Time

VLLSET ILLSET tBOOT

Relative to CSREF CDELAY = 10 nF
−250 −10

VID INPUTS

Input Low Voltage

VIL VID
ORDERING GUIDE

Model

Temperature Range

ADP3192JCPZ-RL1 0°C to 85°C
1 Z = Pb-free part.

Package Description
Package Option Ordering Quantity
40-Lead Frame Chip Scale Package [LFCSP_VQ] CP-40
2,500
2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

D06093-0-6/06 0

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Datasheet ID: ADP3192JCPZ-RL 517856