74F377SC Datasheet

74F377 Octal D-Type Flip-Flop with Clock Enable

Part Datasheet
74F377SC 74F377SC 74F377SC (pdf)
Related Parts Information
74F377SJ 74F377SJ 74F377SJ
74F377SJX 74F377SJX 74F377SJX
74F377SCX 74F377SCX 74F377SCX
74F377PC 74F377PC 74F377PC
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74F377 Octal D-Type Flip-Flop with Clock Enable
74F377 Octal D-Type Flip-Flop with Clock Enable

The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously, when the Clock Enable CE is LOW.

The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
s Ideal for addressable register applications s Clock enable for address and data synchronization
applications s Eight edge-triggered D-type flip-flops s Buffered common clock s See 74F273 for master reset version s See 74F373 for transparent latch version s See 74F374 for 3-STATE version
Ordering Code:

Order Number Package Number

Package Description

20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide

20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide

20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” tot he ordering code.

Logic Symbols

Connection Diagram

2000 Fairchild Semiconductor Corporation DS009525

Unit Loading/Fan Out

Pin Names


Data Inputs Clock Enable Active LOW Clock Pulse Input Data Outputs

Mode Select-Function Table


Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA


Operating Mode

Load “1” Load “0” Hold

Do Nothing

H = HIGH Voltage Level h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition L = LOW Voltage Level I = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
= Immaterial = LOW-to-HIGH Clock Transition

Logic Diagram


No Change

No Change

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output
in HIGH State with VCC = 0V Standard Output 3-STATE Output
−0.5V to VCC −0.5V to +5.5V

Current Applied to Output
in LOW State Max
More datasheets: HMC758LP3E | 121703-HMC758LP3 | IMB1805T | DMS050260-P5P-SZ | TSL13T | TSL12T | 74F377SJ | 74F377SJX | 74F377SCX | 74F377PC

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Datasheet ID: 74F377SC 513325