ADP3189JCPZ-RL

ADP3189JCPZ-RL Datasheet

8-Bit Programmable 2- to 5-Phase Synchronous Buck Controller ADP3189

Part	Datasheet
ADP3189JCPZ-RL	ADP3189JCPZ-RL (pdf)

Related Parts	Information
ADP3189JCPZ-R7	ADP3189JCPZ-R7

PDF Datasheet Preview
8-Bit Programmable 2- to 5-Phase Synchronous Buck Controller ADP3189 Selectable 2-, 3-, 4-, or 5-phase operation at up to 1 MHz per phase mV worst-case differential sensing error over temperature Logic-level PWM outputs for interface to external high-power drivers Active current balancing between all output phases Built-in power good/crowbar blanking supports on-the-fly VID code changes Digitally programmable V to V supports both VR10.x and VR11 specifications Programmable short-circuit protection with programmable latch-off delay Desktop PC power supplies for Next generation processors VRM modules The ADP31891 is a highly efficient multi-phase synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. It uses an internal 8-bit DAC to read a voltage identification VID code directly from the processor, which is used to set the output voltage between V and V. This device uses a multi-mode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, 4-, or 5-phase operation, allowing for the construction of up to five complementary buck switching stages. The ADP3189 also includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current, so it is optimally positioned for a system transient. The ADP3189 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power good output that accommodates on-the-fly output voltage changes requested by the CPU. ADP3189 is specified over the extended commercial temperature range of 0°C to +85°C and is available in a 40-lead LFCSP package. 1 Protected by U.S. Patent Number 6,683,441 others pending. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax: 2005 Analog Devices, Inc. All rights reserved. ADP3189 TABLE OF CONTENTS Functional Block Diagram 3 4 Test 7 Absolute Maximum 8 ESD 8 Pin Configuration and Function DescriptionS 9 Typical Performance Characteristics 11 Theory of Operation 12 Start-Up 12 Phase Detection 12 Master Clock 13 Output Voltage Differential Sensing 13 Output Current Sensing 13 Active Impedance Control 13 Current Control Mode and Thermal Balance 13 Voltage Control 14 Delay 14 Soft Start 14 Current Limit, Short Circuit, and Latch-Off Protection....... 15 Dynamic 15 Power Good Monitoring 15 Output Crowbar 16 Output Enable and UVLO 16 Thermal Monitoring 16 Application 22 Setting the Clock Frequency 22 Soft Start Delay Time 22 0 Initial Version Current Limit Latch-Off Delay 22 Inductor Selection 23 Designing an 23 Selecting a Standard Inductor 23 Current Sense 24 Inductor DCR Temperature Correction 24 Load Line 25 Output Offset 26 COUT Selection 26 Power 27 Ramp Resistor 28 COMP Pin Ramp 28 Current Limit SetPoint 29 Feedback Loop Compensation 29 CIN Selection and Input Current di/dt Reduction.................. 31 Thermal Monitor Design 31 Tuning the ADP3189 32 DC Loadline Setting 32 AC Loadline 33 Initial Transient Setting 33 Layout and Component Placement 34 General Recommendations 34 Power Circuitry Recommendations 34 Signal Circuitry Recommendations 34 Outline Dimensions 35 Ordering Guide 35 FUNCTIONAL BLOCK DIAGRAM VCC 31 ADP3189 UVLO SHUTDOWN AND BIAS GND 18 850mV DAC + 150mV CSREF DAC 250mV PWRGD 2 DELAY TTSENSE 10 VRHOT 9 VRFAN 8 THERMAL THROTTLING CONTROL ILIMIT 11 DELAY 7 RT RAMPADJ OSCILLATOR CMP SET EN RESET 19 OD 30 PWM1 CURRENT BALANCING CIRCUIT RESET 2-/3-/4-/5-PHASE DRIVER LOGIC RESET 29 PWM2 28 PWM3 CMP RESET 27 PWM4 RESET 26 PWM5 CROWBAR CURRENT LIMIT 25 SW1 24 SW2 23 SW3 22 SW4 21 SW5 CURRENT LIMIT CIRCUIT 17 CSCOMP 15 CSREF 16 CSSUM COMP 5 + PRECISION REFERENCE FBRTN 3 VIDSEL 40 VID DAC VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 ORDERING GUIDE Model ADP3189JCPZ-RL1 1 Z = Pb-free part. Temperature Range Package Description 0°C to 85°C 40-Lead Frame Chip Scale Package [LFCSP_VQ] Package Option CP-40 Ordering Quantity 2500 ADP3189 NOTES 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

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8-Bit Programmable 2- to 5-Phase Synchronous Buck Controller ADP3189

Selectable 2-, 3-, 4-, or 5-phase operation at up to 1 MHz per phase
mV worst-case differential sensing error over temperature

Logic-level PWM outputs for interface to external high-power drivers

Active current balancing between all output phases Built-in power good/crowbar blanking supports on-the-fly

VID code changes Digitally programmable V to V supports
both VR10.x and VR11 specifications Programmable short-circuit protection with programmable
latch-off delay

Desktop PC power supplies for Next generation processors VRM modules

The ADP31891 is a highly efficient multi-phase synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. It uses an internal 8-bit DAC to read a voltage identification VID code directly from the processor, which is used to set the output voltage between V and V.

This device uses a multi-mode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relationship of the output signals can be programmed to provide 2-, 3-, 4-, or 5-phase operation, allowing for the construction of up to five complementary buck switching stages.

The ADP3189 also includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current, so it is optimally positioned for a system transient. The ADP3189 also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power good output that accommodates on-the-fly output voltage changes requested by the CPU.

ADP3189 is specified over the extended commercial temperature range of 0°C to +85°C and is available in a 40-lead LFCSP package.
1 Protected by U.S. Patent Number 6,683,441 others pending.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel:

Fax:
2005 Analog Devices, Inc. All rights reserved.

ADP3189

TABLE OF CONTENTS

Functional Block Diagram 3 4 Test 7 Absolute Maximum 8

ESD 8 Pin Configuration and Function DescriptionS 9 Typical Performance Characteristics 11 Theory of Operation 12

Start-Up 12 Phase Detection 12 Master Clock 13 Output Voltage Differential Sensing 13 Output Current Sensing 13 Active Impedance Control 13 Current Control Mode and Thermal Balance 13 Voltage Control 14 Delay 14 Soft Start 14 Current Limit, Short Circuit, and Latch-Off Protection....... 15 Dynamic 15 Power Good Monitoring 15 Output Crowbar 16 Output Enable and UVLO 16 Thermal Monitoring 16 Application 22 Setting the Clock Frequency 22 Soft Start Delay Time 22
0 Initial Version

Current Limit Latch-Off Delay 22 Inductor Selection 23 Designing an 23

Selecting a Standard Inductor 23 Current Sense 24 Inductor DCR Temperature Correction 24 Load Line 25 Output Offset 26 COUT Selection 26 Power 27 Ramp Resistor 28 COMP Pin Ramp 28 Current Limit SetPoint 29 Feedback Loop Compensation 29 CIN Selection and Input Current di/dt Reduction.................. 31 Thermal Monitor Design 31 Tuning the ADP3189 32
DC Loadline Setting 32 AC Loadline 33 Initial Transient Setting 33 Layout and Component Placement 34 General Recommendations 34 Power Circuitry Recommendations 34 Signal Circuitry Recommendations 34 Outline Dimensions 35 Ordering Guide 35

FUNCTIONAL BLOCK DIAGRAM

VCC 31

ADP3189

UVLO SHUTDOWN

AND BIAS

GND 18
850mV

DAC + 150mV CSREF

DAC 250mV

PWRGD 2

DELAY

TTSENSE 10 VRHOT 9 VRFAN 8

THERMAL THROTTLING

CONTROL

ILIMIT 11 DELAY 7

RT RAMPADJ

OSCILLATOR CMP

SET EN RESET
19 OD 30 PWM1

CURRENT BALANCING

CIRCUIT

RESET 2-/3-/4-/5-PHASE DRIVER LOGIC

RESET
29 PWM2 28 PWM3

CMP RESET
27 PWM4

RESET
26 PWM5

CROWBAR

CURRENT LIMIT
25 SW1 24 SW2 23 SW3 22 SW4 21 SW5

CURRENT LIMIT

CIRCUIT
17 CSCOMP 15 CSREF 16 CSSUM

COMP 5
+ PRECISION REFERENCE

FBRTN 3

VIDSEL 40

VID DAC

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
ORDERING GUIDE

Model ADP3189JCPZ-RL1
1 Z = Pb-free part.

Temperature Range Package Description
0°C to 85°C
40-Lead Frame Chip Scale Package [LFCSP_VQ]

Package Option CP-40
Ordering Quantity
2500

ADP3189 NOTES
2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ADP3189JCPZ-RL Datasheet file may be downloaded here without warranties.

Datasheet ID: ADP3189JCPZ-RL 517855