DM74LS90N

DM74LS90N Datasheet

DM74LS90 Decade and Binary Counters

Part	Datasheet
DM74LS90N	DM74LS90N (pdf)

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DM74LS90 Decade and Binary Counters DM74LS90 Decade and Binary Counters Each of these monolithic counters contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the count cycle length is divide-by-five for the DM74LS90. All of these counters have a gated zero reset and the DM74LS90 also has gated set-to-nine inputs for use in BCD nine’s complement applications. To use their maximum count length decade or four bit binary , the B input is connected to the QA output. The input count pulses are applied to input A and the outputs are as described in the appropriate truth table. A symmetrical divide-by-ten count can be obtained from the DM74LS90 counters by connecting the QD output to the A input and applying the input count to the B input which gives a divide-by-ten square wave at output QA. s Typical power dissipation 45 mW s Count frequency 42 MHz Ordering Code: Order Number Package Number Package Description DM74LS90M M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow DM74LS90N N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Reset/Count Truth Table R0 1 H X L X Reset Inputs R0 2 R9 1 R9 2 X L H L X L X Output QD QC QB QA LLLL HL LH COUNT 2000 Fairchild Semiconductor Corporation DS006381 DM74LS90 Function Tables BCD Count Sequence Note 1 Count Output Count 0 1 2 3 4 5 6 7 8 9 Bi-Quinary 5-2 Note 2 Output H = HIGH Level L = LOW Level X = Don’t Care Note 1 Output QA is connected to input B for BCD count. Note 2 Output QD is connected to input A for bi-quinary count. Note 3 Output QA is connected to input B. Logic Diagram The J and K inputs shown without connection are for reference only and are functionally at a high level. DM74LS90 Absolute Maximum Ratings Note 4 Supply Voltage Input Voltage Reset Input Voltage A or B Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0°C to +70°C −65°C to +150°C Note 4 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions VCC VIH VIL IOH IOL fCLK Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency Note 5 fCLK Clock Frequency Note 6 Pulse Width Note 5 Pulse Width Note 6 tREL Reset Release Time Note 5 tREL Reset Release Time Note 6 Free Air Operating Temperature

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DM74LS90 Decade and Binary Counters

DM74LS90 Decade and Binary Counters

Each of these monolithic counters contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the count cycle length is divide-by-five for the DM74LS90.

All of these counters have a gated zero reset and the DM74LS90 also has gated set-to-nine inputs for use in BCD nine’s complement applications.

To use their maximum count length decade or four bit binary , the B input is connected to the QA output. The input count pulses are applied to input A and the outputs are as described in the appropriate truth table. A symmetrical divide-by-ten count can be obtained from the DM74LS90 counters by connecting the QD output to the A input and applying the input count to the B input which gives a divide-by-ten square wave at output QA.
s Typical power dissipation 45 mW s Count frequency 42 MHz
Ordering Code:

Order Number Package Number

Package Description

DM74LS90M

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow

DM74LS90N

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Reset/Count Truth Table

R0 1 H X L X

Reset Inputs

R0 2 R9 1

R9 2 X L H L X L X

Output QD QC QB QA LLLL HL LH

COUNT
2000 Fairchild Semiconductor Corporation DS006381

DM74LS90

Function Tables

BCD Count Sequence Note 1

Count

Output

Count
0 1 2 3 4 5 6 7 8 9

Bi-Quinary 5-2 Note 2

Output

H = HIGH Level L = LOW Level X = Don’t Care Note 1 Output QA is connected to input B for BCD count.

Note 2 Output QD is connected to input A for bi-quinary count.

Note 3 Output QA is connected to input B.

Logic Diagram

The J and K inputs shown without connection are for reference only and are functionally at a high level.

DM74LS90

Absolute Maximum Ratings Note 4

Supply Voltage Input Voltage Reset Input Voltage A or B Operating Free Air Temperature Range Storage Temperature Range
7V 5.5V 0°C to +70°C −65°C to +150°C

Note 4 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

VCC VIH VIL IOH IOL fCLK

Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency Note 5
fCLK

Clock Frequency Note 6

Pulse Width Note 5

Pulse Width Note 6
tREL

Reset Release Time Note 5
tREL

Reset Release Time Note 6

Free Air Operating Temperature

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Datasheet ID: DM74LS90N 513816