ADP3162JR-REEL

ADP3162JR-REEL Datasheet


ADP3162

Part Datasheet
ADP3162JR-REEL ADP3162JR-REEL ADP3162JR-REEL (pdf)
Related Parts Information
ADP3162JRZ-REEL7 ADP3162JRZ-REEL7 ADP3162JRZ-REEL7
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FEATURES ADOPT Optimal Positioning Technology for Superior

Load Transient Response and Fewest Output Capacitors Complies with VRM with Lowest System Cost Active Current Balancing Between Both Output Phases 5-Bit Digitally Programmable V to V Output Dual Logic-Level PWM Outputs for Interface to External High-Power Drivers Total Output Accuracy Over Temperature Current-Mode Operation Short Circuit Protection Power Good Output Overvoltage Protection Crowbar Protects Microprocessors with No Additional External Components

APPLICATIONS Desktop PC Power Supplies for:

Intel Tualatin Processors VRM Modules
5-Bit Programmable 2-Phase Synchronous Buck Controller

ADP3162

FUNCTIONAL BLOCK DIAGRAM

REF GND

COMP

UVLO & BIAS
3.0V REFERENCE

SET RESET CROWBAR
2-PHASE DRIVER LOGIC

CMP3

DAC+24%

OSCILLATOR

ADP3162

CMP CMP2

CMP CMP1

VID DAC

PWM1 PWM2

PWRGD

CS+ FB

GENERAL DESCRIPTION The ADP3162 is a highly efficient dual output synchronous buck switching regulator controller optimized for converting a 5 V or 12 V main supply into the core supply voltage required by high-performance processors such as Tualatin. The ADP3162 uses an internal 5-bit DAC to read a voltage identification VID code directly from the processor, which is used to set the output voltage between V and V. The ADP3162 uses a current mode PWM architecture to drive two logic-level outputs at a programmable switching frequency that can be optimized for VRM size and efficiency. The output signals are 180 degrees out of phase, allowing for the construction of two complementary buck switching stages. These two stages share the dc output current to reduce overall output voltage ripple. An active current balancing function ensures that both phases carry equal portions of the total load current, even under large transient loads, to minimize the size of the inductors.

VID3 VID2 VID1 VID0 VID25

The ADP3162 also uses a unique supplemental regulation technique called active voltage positioning to enhance load transient performance. Active voltage positioning results in a dc/dc converter that meets the stringent output voltage specifications for high performance processors, with the minimum number of output capacitors and smallest footprint. Unlike voltage-mode and standard current-mode architectures, active voltage positioning adjusts the output voltage as a function of the load current so that it is always optimally positioned for a system transient. The ADP3162 also provides accurate and reliable short circuit protection and adjustable current limiting.

The ADP3162 is specified over the commercial temperature range of 0°C to 70°C and is available in a 16-lead narrow body SOIC package.

ADOPT is a trademark of Analog Devices, Inc.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel 781/329-4700

Fax 781/326-8703

Analog Devices, Inc., 2001

VCC = 12 V, IREF = 150 TA = to unless otherwise noted.

Parameter

Conditions

Min Typ Max

FEEDBACK INPUT Accuracy V Output V Output V Output Line Regulation Input Bias Current Crowbar Trip Threshold Crowbar Reset Threshold Crowbar Response Time FB Low Foldback Threshold

REFERENCE Output Voltage Output Current

VID INPUTS Input Low Voltage Input High Voltage Input Current Pull-Up Resistance Internal Pull-Up Voltage

IFB VCROWBAR
ORDERING GUIDE

Model

Temperature Package

Range

Package Option

ADP3162JR 0°C to 70°C Narrow Body SOIC R-16A SO-16

PIN CONFIGURATION

VID3 1
16 VCC

VID2 2
15 REF

VID1 3

VID0 4 ADP3162 13 PWM1 TOP VIEW

VID25 5 Not to Scale 12 PWM2

COMP 6
11 CS+
10 PWRGD
9 GND

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function

VID3 Voltage DAC Inputs.
5 VID25

These pins are pulled up to an internal
reference, providing a Logic 1 if left open.

The DAC output programs the FB regula-
tion voltage from V to V.
6 COMP

Error Output and Compensation Point. The voltage at this output programs the output current control level between CS+ and

Feedback Input. Error input for remote sensing of the output voltage.

External capacitor CT connection to ground sets the frequency of the device.
9 GND

Ground. All internal signals of the ADP3162 are referenced to this ground.
10 PWRGD

Open drain output that signals when the output voltage is in the proper operating range.
11 CS+

Current Sense Positive Node. Positive input for the current comparator. The output current is sensed as a voltage at this pin with respect to
12 PWM2

Logic-level output for the Phase 2 driver.
13 PWM1

Logic-level output for the Phase 1 driver.

Current Sense Negative Node. Negative input for the current comparator.
More datasheets: TLIXF30011-865853 | SSIXF30011-875263 | TLIXF30009-865852 | SSIXF30009-875252 | 74F132SJ | 74F132SJX | 74F132PC | 74F132SCX | 74F132SC | ADP3162JRZ-REEL7


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Datasheet ID: ADP3162JR-REEL 517848