74F132PC

74F132PC Datasheet

74F132 Quad 2-Input NAND Schmitt Trigger

Part	Datasheet
74F132PC	74F132PC (pdf)

Related Parts	Information
74F132SJ	74F132SJ
74F132SJX	74F132SJX
74F132SCX	74F132SCX
74F132SC	74F132SC

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74F132 Quad 2-Input NAND Schmitt Trigger 74F132 Quad 2-Input NAND Schmitt Trigger The F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise margin than conventional NAND gates. Each circuit contains a 2-input Schmitt Trigger followed by level shifting circuitry and a standard output struc- ture. The Schmitt Trigger uses positive feedback to effectively speed-up slow input transitions, and provide different input threshold voltages for positive and negative-going transitions. This hysteresis between the positive-going and negative-going input threshold typically 800 mV is determined by resistor ratios and is essentially insensitive to temperature and supply voltage variations. Ordering Code: Order Number Package Number Package Description 74F132SC M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow 74F132SJ M14D 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F132PC N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Unit Loading/Fan Out U.L. Pin Names Description HIGH/LOW An, Bn On Inputs Outputs Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA −1 mA/20 mA Function Table Inputs H = HIGH Voltage Level L = LOW Voltage Level Outputs is a registered trademark of Fairchild Semiconductor Corporation 2000 Fairchild Semiconductor Corporation DS009477 74F132 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2 −30 mA to mA Voltage Applied to Output in HIGH State with VCC = 0V Standard Output 3-STATE Output −0.5V to VCC −0.5V to +5.5V Current Applied to Output in LOW State Max twice the rated IOL mA ESD Last Passing Voltage Min 4000V Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0°C to +70°C +4.5V to +5.5V Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2 Either voltage limit or current limit is sufficient to protect inputs.

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74F132 Quad 2-Input NAND Schmitt Trigger
74F132 Quad 2-Input NAND Schmitt Trigger

The F132 contains four 2-input NAND gates which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise margin than conventional NAND gates.

Each circuit contains a 2-input Schmitt Trigger followed by level shifting circuitry and a standard output struc-
ture. The Schmitt Trigger uses positive feedback to effectively speed-up slow input transitions, and provide different input threshold voltages for positive and negative-going transitions. This hysteresis between the positive-going and negative-going input threshold typically 800 mV is determined by resistor ratios and is essentially insensitive to temperature and supply voltage variations.
Ordering Code:

Order Number Package Number

Package Description
74F132SC

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow
74F132SJ

M14D
14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F132PC

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram

IEEE/IEC

Unit Loading/Fan Out

U.L. Pin Names Description

HIGH/LOW

An, Bn On

Inputs Outputs

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA −1 mA/20 mA

Function Table

Inputs

H = HIGH Voltage Level L = LOW Voltage Level

Outputs
is a registered trademark of Fairchild Semiconductor Corporation
2000 Fairchild Semiconductor Corporation DS009477
74F132

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output
in HIGH State with VCC = 0V Standard Output 3-STATE Output
−0.5V to VCC −0.5V to +5.5V

Current Applied to Output
in LOW State Max
twice the rated IOL mA

ESD Last Passing Voltage Min
4000V

Recommended Operating Conditions

Free Air Ambient Temperature Supply Voltage
0°C to +70°C +4.5V to +5.5V

Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.

Note 2 Either voltage limit or current limit is sufficient to protect inputs.

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Datasheet ID: 74F132PC 513273