FSTUD32450GX

FSTUD32450GX Datasheet

FSTUD32450 Configurable 4-Bit to 40-Bit Bus Switch with Undershoot Protection and Selectable Level Shifting

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FSTUD32450GX	FSTUD32450GX (pdf)

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FSTUD32450 Configurable 4-Bit to 40-Bit Bus Switch with Undershoot Protection and Selectable Level Shifting FSTUD32450 Configurable 4-Bit to 40-Bit Bus Switch with Undershoot Protection and Selectable Level Shifting The Fairchild Universal Bus Switch FSTUD32450 provides 4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit...40-bit of high-speed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. The FSTUD32450 is designed to allow “customer” configuration control of the enable connections. The device can be organized as either a ten 4-bit, eight 5-bit, four 10-bit, two 20-bit or one 40-bit enabled bus switch. Also achievable are 8-bit and 16-bit enabled configurations see Functional Description . The device's bit configuration is controlled through select pin logic. see Truth Table . When OEx is LOW, Port Ax is connected to Port Bx. When OEx is HIGH, the switch is OPEN. The A and B Ports are protected against undershoot to support an extended range to 2.0V below ground. Fairchild's integrated Undershoot Hardened Circuit senses undershoot at the I/O, and responds by preventing voltage differentials from developing and turning the switch on. Another innovative device feature is the addition of a level shifting select pin, “S2 and S5”. When S2 and S5 are LOW, the device behaves as a standard N-MOS switch. When S2 and S5 are HIGH, a diode to VCC is integrated into the circuit allowing for level shifting between 5V inputs and 3.3V outputs. s Undershoot protected to A and B Ports s Voltage level shifting s 4 switch connection between two ports s Minimal propagation delay through the switch s Low lCC s Zero bounce in flow-through mode s Control inputs compatible with TTL level s See Applications Notes AN-5008 and AN-5021 for UHC details s Packaged in plastic Fine-Pitch Ball Grid Array FBGA Applications Note Select pins S0, S1, S2, S3, S4 and S5 are intended to be used as static user configurable control pins. The AC performance of these pins has not been characterized or tested. Switching of these select pins during system operation may temporarily disrupt output logic states and/or enable pin controls. 40-bit configuration can be achieved by connecting the OE1 and the OE6 pins to together. Ordering Code: Order Number Package Number Package Description FSTUD32450G Note 1 Note 2 BGA114A 114-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide Note 1 Ordering code “G” indicates Trays. Note 2 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. is a registered trademark of Fairchild Semiconductor Corporation. 2005 Fairchild Semiconductor Corporation DS500447 FSTUD32450 Connection Diagram Pin Assignment for FBGA Top Thru View Pin Descriptions Pin Name OE1, OE2, OE3, OE4, OE5, OE6, OE7, OE8 OE9, OE10 1A, 2A, 3A, 4A 1B, 2B, 3B, 4B S0, S1, S3, S4 S2, S5 Description Bus Switch Enables Bus A Bus B Bit Configuration Enables Level Shifting Diode Enables FBGA Pin Assignments 1A4 1A2 OE1 OE2 1B2 1B4 1A6 1A5 1A1 1B1 1B5 1B6 1A8 1A7 1A3 1B3 1B7 1B8 D 1A10 1A9 GND OE5 1B9 1B10 2A2 2A1 VCC 2B1 2B2 2A4 2A3 S2 2B3 2B4 2A6 2A5 VCC GND 2B5 2B6 2A8 2A7 GND 2B7 2B8 J 2A10 2A9 GND 2B9 2B10 K OE4 OE8 GND OE9 OE3 L 3A10 3A9 GND 3B9 3B10 M 3A8 3A7 GND 3B7 3B8 3A6 3A5 GND VCC 3B5 3B6 3A4 3A3 S4 3B3 3B4 3A2 3A1 VCC S3 3B1 3B2 T 4A10 4A9 OE10 GND 4B9 4B10 4A8 4A7 4A3 4B3 4B7 4B8 4A6 4A5 4A1 4B1 4B5 4B6 4A4 4A2 OE7 OE6 4B2 4B4 FSTUD32450 Logic Diagrams 20-Bit Configuration 10-Bit Configuration FSTUD32450 5-Bit Configuration

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FSTUD32450 Configurable 4-Bit to 40-Bit Bus Switch with Undershoot Protection and Selectable Level Shifting

FSTUD32450

Configurable 4-Bit to 40-Bit Bus Switch with Undershoot Protection and Selectable Level Shifting

The Fairchild Universal Bus Switch FSTUD32450 provides 4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit...40-bit of high-speed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise.

The FSTUD32450 is designed to allow “customer” configuration control of the enable connections. The device can be organized as either a ten 4-bit, eight 5-bit, four 10-bit, two 20-bit or one 40-bit enabled bus switch. Also achievable are 8-bit and 16-bit enabled configurations see Functional Description . The device's bit configuration is controlled through select pin logic. see Truth Table . When OEx is LOW, Port Ax is connected to Port Bx. When OEx is HIGH, the switch is OPEN.

The A and B Ports are protected against undershoot to support an extended range to 2.0V below ground. Fairchild's integrated Undershoot Hardened Circuit senses undershoot at the I/O, and responds by preventing voltage differentials from developing and turning the switch on.

Another innovative device feature is the addition of a level shifting select pin, “S2 and S5”. When S2 and S5 are LOW, the device behaves as a standard N-MOS switch. When S2 and S5 are HIGH, a diode to VCC is integrated into the circuit allowing for level shifting between 5V inputs and 3.3V outputs.
s Undershoot protected to A and B Ports s Voltage level shifting s 4 switch connection between two ports s Minimal propagation delay through the switch s Low lCC s Zero bounce in flow-through mode s Control inputs compatible with TTL level s See Applications Notes AN-5008 and AN-5021 for UHC
details s Packaged in plastic Fine-Pitch Ball Grid Array FBGA

Applications Note

Select pins S0, S1, S2, S3, S4 and S5 are intended to be used as static user configurable control pins. The AC performance of these pins has not been characterized or tested. Switching of these select pins during system operation may temporarily disrupt output logic states and/or enable pin controls. 40-bit configuration can be achieved by connecting the OE1 and the OE6 pins to together.
Ordering Code:

Order Number Package Number

Package Description

FSTUD32450G Note 1 Note 2

BGA114A
114-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide
Note 1 Ordering code “G” indicates Trays.
Note 2 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
is a registered trademark of Fairchild Semiconductor Corporation. 2005 Fairchild Semiconductor Corporation DS500447

FSTUD32450

Connection Diagram

Pin Assignment for FBGA

Top Thru View

Pin Descriptions

Pin Name

OE1, OE2, OE3, OE4, OE5, OE6, OE7, OE8 OE9, OE10 1A, 2A, 3A, 4A 1B, 2B, 3B, 4B S0, S1, S3, S4 S2, S5

Description Bus Switch Enables

Bus A Bus B Bit Configuration Enables Level Shifting Diode Enables

FBGA Pin Assignments
1A4 1A2 OE1 OE2 1B2 1B4
1A6 1A5 1A1 1B1 1B5 1B6
1A8 1A7 1A3 1B3 1B7 1B8

D 1A10 1A9 GND OE5 1B9 1B10
2A2 2A1

VCC 2B1 2B2
2A4 2A3

S2 2B3 2B4
2A6 2A5 VCC GND 2B5 2B6
2A8 2A7 GND 2B7 2B8

J 2A10 2A9 GND 2B9 2B10

K OE4 OE8 GND OE9 OE3

L 3A10 3A9 GND 3B9 3B10

M 3A8 3A7 GND 3B7 3B8
3A6 3A5 GND VCC 3B5 3B6
3A4 3A3

S4 3B3 3B4
3A2 3A1 VCC

S3 3B1 3B2

T 4A10 4A9 OE10 GND 4B9 4B10
4A8 4A7 4A3 4B3 4B7 4B8
4A6 4A5 4A1 4B1 4B5 4B6
4A4 4A2 OE7 OE6 4B2 4B4

FSTUD32450

Logic Diagrams
20-Bit Configuration
10-Bit Configuration

FSTUD32450
5-Bit Configuration

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Datasheet ID: FSTUD32450GX 515563