FSTUD16450MTD

FSTUD16450MTD Datasheet


FSTUD16450 Configurable 4-Bit to 20-Bit Bus Switch with -2V Undershoot Protection and Selectable Level Shifting

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FSTUD16450MTD FSTUD16450MTD FSTUD16450MTD (pdf)
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FSTUD16450 Configurable 4-Bit to 20-Bit Bus Switch with -2V Undershoot Protection and Selectable Level Shifting

FSTUD16450 Configurable 4-Bit to 20-Bit Bus Switch with -2V Undershoot Protection and Selectable Level Shifting

The Fairchild Universal Bus Switch FSTUD16450 provides 4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit of high-speed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise.

The FSTUD16450 is designed to allow “customer” configuration control of the enable connections. The device is organized as either a 4-bit, 5-bit, 10-bit or 20-bit bus switch. 8-bit and 16-bit configurations are also achievable see Functional Description . The device's bit configuration is chosen through select pin logic. see Truth Table . When OEx is LOW, Port Ax is connected to Port Bx. When OEx is HIGH, the switch is OPEN.

The A and B Ports are “undershoot hardened” with protection to support an extended range to 2.0V below ground. Fairchild's integrated “Undershoot Hardened Circuit” UHC senses undershoot at the I/O's, and responds by preventing voltage differentials from developing and turning on the switch.

Another key device feature is the addition of a level shifting select pin, “S2”. When S2 is LOW, the device behaves as a standard N-MOS switch. When S2 is HIGH, a diode to VCC is integrated into the circuit allowing for level shifting between 5V inputs and 3.3V outputs.
s Undershoot hardened to −2V A and B Ports s Voltage level shifting s switch connection between two ports s Minimal propagation delay through the switch s Low lCC s Zero bounce in flow-through mode s Control inputs compatible with TTL level s See Applications Note AN-5008 for details s Also packaged in plastic Fine-Pitch Ball Grid Array

FBGA Preliminary

Applications Note

Select pins S0, S1, S2 are intended to be used as static user configurable control pins. The AC performance of these pins has not been characterized or tested. Switching of these select pins during system operation may temporarily disrupt output logic states and/or enable pin controls.
Ordering Code:

Order Number Package Number

Package Description

FSTUD16450GX Note 1

BGA54A Preliminary
54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide [Tape and Reel]

FSTUD16450MTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Note 1 BGA package available in Tape and Reel only.
is a trademark of Fairchild Semiconductor Corporation.
2001 Fairchild Semiconductor Corporation DS500391

FSTUD16450

Connection Diagrams

Pin Assignment for TSSOP

Pin Descriptions

Pin Name

OE1, OE2 1A, 2A 1B, 2B S0, S1 S2 NC

Bus Switch Enables Bus A Bus B

Bit Configuration Enables Level Shifting Diode Enable

No Connect

FBGA Pin Assignments
1A3 1A2 OE1 OE2 1B2 1B3
1A5 1A4 1A1 1B1 1B4 1B5
1A7 1A6 GND OE5 1B6 1B7
1A9 1A8 GND VCC 1B8 1B9
2A1 1A10 S0 VCC 1B10 2B1
2A3 2A2 S1

S2 2B2 2B3
2A5 2A4 VCC GND 2B4 2B5
2A7 2A6 2A10 2B10 2B6 2B7
2A9 2A8 OE4 OE3 2B8 2B9

Pin Assignment for FBGA

Top Thru View

FSTUD16450

Logic Diagrams
20-Bit Configuration 1
10-Bit Configuration 2
5-Bit Configuration 3
4-Bit Configuration 4

FSTUD16450

Functional Description

The device can also be configured as an 8 and 16-bit device by grounding the unused pins in Configurations 2 and 1 respectively. The 8-bit configuration may also be achieved by tying two of the 4-bit enables from configuration together and tying the remaining enable pin OE HIGH.

Truth Tables X = VCC or GND
see Functional Description

S2 L H

Select Pin Mode

Std. NMOS Switch Level Shifting Diode Enabled

Configuration 1

OE1 L H
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Datasheet ID: FSTUD16450MTD 515562