FQD3P50TF

FQD3P50TF Datasheet


FQD3P50 / FQU3P50

Part Datasheet
FQD3P50TF FQD3P50TF FQD3P50TF (pdf)
Related Parts Information
FQU3P50TU FQU3P50TU FQU3P50TU
PDF Datasheet Preview
FQD3P50 / FQU3P50

FQD3P50 / FQU3P50
500V P-Channel MOSFET

January 2009

These P-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for electronic lamp ballast based on complimentary half bridge.

D-PAK

FQD Series
• -2.1A, -500V, RDS on = = -10 V
• Low gate charge typical 18 nC
• Low Crss typical pF
• Fast switching
• 100% avalanche tested
• Improved dv/dt capability
• RoHS Compliant

I-PAK

FQU Series
● ●

Absolute Maximum Ratings TC = 25°C unless otherwise noted

Symbol VDSS ID

IDM VGSS EAS IAR EAR dv/dt PD

TJ, TSTG TL

Parameter

Drain-Source Voltage

Drain Current
- Continuous TC = 25°C - Continuous TC = 100°C

Drain Current - Pulsed

Note 1

Gate-Source Voltage

Single Pulsed Avalanche Energy

Note 2

Avalanche Current

Note 1

Repetitive Avalanche Energy

Note 1

Peak Diode Recovery dv/dt

Note 3

Power Dissipation TA = 25°C * Power Dissipation TC = 25°C
- Derate above 25°C

Operating and Storage Temperature Range

Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds

Thermal Characteristics

Parameter Thermal Resistance, Junction-to-Case Thermal Resistance, Junction-to-Ambient * Thermal Resistance, Junction-to-Ambient
* When mounted on the minimum pad size recommended PCB Mount
2009 Fairchild Semiconductor Internati

FQD3P50 / FQU3P50 -500 ± 30 250 50
-55 to +150

Units V A V mJ A mJ
More datasheets: HSMD-C150 | HSMG-C177 | HSMY-C110 | HSMG-C110 | HSMH-C110 | HSMS-C150 | HSMG-C197 | HSMD-C190 | 28388 | FQU3P50TU


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Datasheet ID: FQD3P50TF 515243