FIN1532M

FIN1532M Datasheet

FIN1532 5V LVDS 4-Bit High Speed Differential Receiver

Part	Datasheet
FIN1532M	FIN1532M (pdf)

Related Parts	Information
FIN1532MX_NF40	FIN1532MX_NF40
FIN1532MTC	FIN1532MTC

PDF Datasheet Preview
FIN1532 5V LVDS 4-Bit High Speed Differential Receiver FIN1532 5V LVDS 4-Bit High Speed Differential Receiver This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data. The FIN1532 can be paired with its companion driver, the FIN1531, or any other LVDS driver. s Greater than 400Mbs data rate s 5V power supply operation s ns maximum differential pulse skew s 3 ns maximum propagation delay s Low power dissipation s Power-Off protection for inputs and outputs s Fail safe protection for open-circuit, shorted and termi- nated receiver inputs s Meets or exceeds the TIA/EIA-644 LVDS standard s Pin compatible with equivalent RS-422 and PECL devices s 16-Lead SOIC and TSSOP packages save space Ordering Code: Order Number Package Number Package Description FIN1532M M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow FIN1532MTC MTC16 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pin Descriptions Connection Diagram Pin Name ROUT1, ROUT2, ROUT3, ROUT4 LVTTL Data Outputs RIN1+, RIN2+, RIN3+, RIN4+ Non-inverting LVDS Inputs RIN1−, RIN2−, RIN3−, RIN4− Inverting LVDS Inputs Driver Enable Pin EN VCC GND Inverting Driver Enable Pin Power Supply Ground Function Table Input Outputs RIN+ RIN+ ROUT Fail Safe Condition Fail Safe Condition H = HIGH Logic Level L = LOW Logic Level X = Don’t Care Z = High Impedance Fail Safe = Open, Shorted, Terminated Top View 2001 Fairchild Semiconductor Corporation DS500504 FIN1532 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Voltage VIN Enable Inputs Receiver Inputs DC Output Voltage VOUT DC Output Current IO Storage Temperature Range TSTG Max Junction Temperature TJ Lead Temperature TL Soldering, 10 seconds ESD Human Body Model ESD Machine Model V to +6 V V to +6 V to +6 V to +6 V 16 mA −65°C to +150°C 150°C 260°C 8000 V 300 V Recommended Operating Conditions Supply Voltage VCC Input Voltage VIN Enable Inputs Receiver Inputs V to V 0 to VCC 0 to V

PDF Datasheet Preview

FIN1532 5V LVDS 4-Bit High Speed Differential Receiver

FIN1532 5V LVDS 4-Bit High Speed Differential Receiver

This quad receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data.

The FIN1532 can be paired with its companion driver, the FIN1531, or any other LVDS driver.
s Greater than 400Mbs data rate s 5V power supply operation s ns maximum differential pulse skew s 3 ns maximum propagation delay s Low power dissipation s Power-Off protection for inputs and outputs s Fail safe protection for open-circuit, shorted and termi-
nated receiver inputs s Meets or exceeds the TIA/EIA-644 LVDS standard s Pin compatible with equivalent RS-422
and PECL devices s 16-Lead SOIC and TSSOP packages save space
Ordering Code:

Order Number Package Number

Package Description

FIN1532M

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

FIN1532MTC

MTC16
16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pin Descriptions

Connection Diagram

Pin Name

ROUT1, ROUT2, ROUT3, ROUT4 LVTTL Data Outputs

RIN1+, RIN2+, RIN3+, RIN4+ Non-inverting LVDS Inputs

RIN1−, RIN2−, RIN3−, RIN4− Inverting LVDS Inputs

Driver Enable Pin

EN VCC GND

Inverting Driver Enable Pin Power Supply Ground

Function Table

Input

Outputs

RIN+

RIN+

ROUT

Fail Safe Condition

Fail Safe Condition

H = HIGH Logic Level L = LOW Logic Level X = Don’t Care Z = High Impedance Fail Safe = Open, Shorted, Terminated

Top View
2001 Fairchild Semiconductor Corporation DS500504

FIN1532

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Voltage VIN

Enable Inputs Receiver Inputs

DC Output Voltage VOUT DC Output Current IO Storage Temperature Range TSTG Max Junction Temperature TJ Lead Temperature TL

Soldering, 10 seconds

ESD Human Body Model

ESD Machine Model

V to +6 V

V to +6 V to +6 V to +6 V
16 mA −65°C to +150°C
150°C
260°C 8000 V
300 V

Recommended Operating Conditions

Supply Voltage VCC Input Voltage VIN

Enable Inputs

Receiver Inputs

V to V
0 to VCC 0 to V

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Datasheet ID: FIN1532M 514679