FDG6302P

FDG6302P Datasheet

FDG6302P Dual P-Channel, Digital FET

Part	Datasheet
FDG6302P	FDG6302P (pdf)

PDF Datasheet Preview
July 1999 FDG6302P Dual P-Channel, Digital FET These dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. -25 V, A continuous, A peak. RDS ON = 10 VGS= V, RDS ON = 13 VGS= V. Very low level gate drive requirements allowing direct operation in 3 V circuits VGS th < V . Gate-Source Zener for ESD ruggedness >6kV Human Body Model . Compact industry standard SC70-6 surface mount package. SC70-6 SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 S2 G2 D1 1 or 4 * 2 or 5 SC70-6 S1 3 or 6 The pinouts are symmetrical pin 1 and 4 are interchangeable. Units inside the carrier can be of either orientation and will not affect the functionality of the device. Absolute Maximum Ratings TA = 25°C unless otherwise noted Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage Drain/Output Current - Continuous - Pulsed Maximum Power Dissipation Note 1 TJ,TSTG Operating and Storage Temperature Range Electrostatic Discharge Rating MIL-STD-883D Human Body Model 100 pF / 1500 THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Note 1 FDG6302P -25 -8 -55 to 150 SOT-223 6 or 3 5 or 2 4 or 1 Units V A W °C kV °C/W

PDF Datasheet Preview

July 1999

FDG6302P Dual P-Channel, Digital FET

These dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs.
-25 V, A continuous, A peak. RDS ON = 10 VGS= V, RDS ON = 13 VGS= V.

Very low level gate drive requirements allowing direct operation in 3 V circuits VGS th < V .

Gate-Source Zener for ESD ruggedness >6kV Human Body Model .

Compact industry standard SC70-6 surface mount package.

SC70-6

SOT-23

SuperSOTTM-6

SuperSOTTM-8

SO-8

S2 G2 D1
1 or 4 *
2 or 5

SC70-6 S1
3 or 6
*The pinouts are symmetrical pin 1 and 4 are interchangeable.

Units inside the carrier can be of either orientation and will not affect the functionality of the device.

Absolute Maximum Ratings TA = 25°C unless otherwise noted

Symbol Parameter

VDSS

Drain-Source Voltage

VGSS

Gate-Source Voltage

Drain/Output Current - Continuous
- Pulsed

Maximum Power Dissipation

Note 1

TJ,TSTG Operating and Storage Temperature Range

Electrostatic Discharge Rating MIL-STD-883D

Human Body Model 100 pF / 1500

THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient Note 1

FDG6302P -25 -8
-55 to 150

SOT-223
6 or 3 5 or 2
4 or 1 *

Units V A W °C kV
°C/W

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Datasheet ID: FDG6302P 514169