CY7C1318CV18-278BZXC

CY7C1318CV18-278BZXC Datasheet

CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18

Part	Datasheet
CY7C1318CV18-278BZXC	CY7C1318CV18-278BZXC (pdf)

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CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 18-Mbit DDR-II SRAM 2-Word Burst Architecture Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 • 300-MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency • Double Data Rate DDR interfaces data transferred at 600 MHz 300 MHz • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Two input clocks for output data C and C to minimize clock-skew and flight-time mismatches • Echo clocks CQ and CQ simplify data capture in high-speed systems • Synchronous internally self-timed writes • DDR-II operates with cycle read latency when the DLL is enabled • Operates like a DDR-I device with 1 cycle read latency in DLL off mode • 1.8V core power supply with HSTL inputs and outputs • Variable drive HSTL output buffers • Expanded HSTL output voltage • Available in 165-ball FBGA package 13 x 15 x mm • Offered in both lead-free and non lead-free packages • JTAG 1149.1-compatible test access port • Delay Lock Loop DLL for accurate data placement Configurations CY7C1316CV18 2M x 8 CY7C1916CV18 2M x 9 CY7C1318CV18 1M x 18 CY7C1320CV18 512K x 36 The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18 and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1316CV18 and two 9-bit words in the case of CY7C1916CV18 that burst sequentially into or out of the device. The burst counter always starts with a “0” internally in the case of CY7C1316CV18 and CY7C1916CV18. On CY7C1318CV18 and CY7C1320CV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1318CV18 and two 36-bit words in the case of CY7C1320CV18 sequentially into or out of the device. Asynchronous inputs include output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Selection Guide Maximum Operating Frequency Maximum Operating Current 300 MHz 300 600 278 MHz 278 580 250 MHz 250 550 200 MHz 200 500 167 MHz 167 450 Unit MHz mA Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Logic Block Diagram CY7C1316CV18 CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 A 19:0 20 Address Register DOFF CLK Gen. VREF R/W NWS[1:0] Control Logic Write Reg Write Reg 1M x 8 Array 1M x 8 Array Read Data Reg. 16 8 Logic Block Diagram CY7C1916CV18 Write Add. Decode Read Add. Decode Output Logic Ordering Information “Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered”. Speed MHz Ordering Code Package Diagram Package Type Operating Range 300 CY7C1316CV18-300BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1318CV18-300BZC CY7C1320CV18-300BZC CY7C1916CV18-300BZC 300 CY7C1316CV18-300BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free Commercial CY7C1318CV18-300BZXC CY7C1320CV18-300BZXC CY7C1916CV18-300BZXC 300 CY7C1316CV18-300BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1318CV18-300BZI CY7C1320CV18-300BZI CY7C1916CV18-300BZI 300 CY7C1316CV18-300BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free Industrial CY7C1318CV18-300BZXI CY7C1320CV18-300BZXI CY7C1916CV18-300BZXI 278 CY7C1316CV18-278BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1318CV18-278BZC CY7C1320CV18-278BZC CY7C1916CV18-278BZC 278 CY7C1316CV18-278BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free Commercial CY7C1318CV18-278BZXC CY7C1320CV18-278BZXC CY7C1916CV18-278BZXC 278 CY7C1316CV18-278BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1318CV18-278BZI CY7C1320CV18-278BZI CY7C1916CV18-278BZI 278 CY7C1316CV18-278BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free Industrial CY7C1318CV18-278BZXI CY7C1320CV18-278BZXI CY7C1916CV18-278BZXI 250 CY7C1316CV18-250BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Ordering Information continued “Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered”. Speed MHz Ordering Code Package Diagram Package Type Operating Range 250 CY7C1316CV18-250BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1318CV18-250BZI CY7C1320CV18-250BZI CY7C1916CV18-250BZI 250 CY7C1316CV18-250BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free Industrial CY7C1318CV18-250BZXI CY7C1320CV18-250BZXI CY7C1916CV18-250BZXI 200 CY7C1316CV18-200BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1318CV18-200BZC CY7C1320CV18-200BZC CY7C1916CV18-200BZC 200 CY7C1316CV18-200BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free Commercial CY7C1318CV18-200BZXC CY7C1320CV18-200BZXC CY7C1916CV18-200BZXC 200 CY7C1316CV18-200BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Industrial CY7C1318CV18-200BZI CY7C1320CV18-200BZI CY7C1916CV18-200BZI 200 CY7C1316CV18-200BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free Industrial CY7C1318CV18-200BZXI CY7C1320CV18-200BZXI CY7C1916CV18-200BZXI 167 CY7C1316CV18-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Commercial CY7C1318CV18-167BZC CY7C1320CV18-167BZC CY7C1916CV18-167BZC 167 CY7C1316CV18-167BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free Commercial CY7C1318CV18-167BZXC CY7C1320CV18-167BZXC CY7C1916CV18-167BZXC 167 CY7C1316CV18-167BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

PDF Datasheet Preview

CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18
18-Mbit DDR-II SRAM 2-Word Burst Architecture

Functional Description
• 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36
• 300-MHz clock for high bandwidth
• 2-Word burst for reducing address bus frequency
• Double Data Rate DDR interfaces
data transferred at 600 MHz 300 MHz
• Two input clocks K and K for precise DDR timing

SRAM uses rising edges only
• Two input clocks for output data C and C to minimize
clock-skew and flight-time mismatches
• Echo clocks CQ and CQ simplify data capture in
high-speed systems
• Synchronous internally self-timed writes
• DDR-II operates with cycle read latency when the

DLL is enabled
• Operates like a DDR-I device with 1 cycle read latency
in DLL off mode
• 1.8V core power supply with HSTL inputs and outputs
• Variable drive HSTL output buffers
• Expanded HSTL output voltage
• Available in 165-ball FBGA package 13 x 15 x mm
• Offered in both lead-free and non lead-free packages
• JTAG 1149.1-compatible test access port
• Delay Lock Loop DLL for accurate data placement

Configurations

CY7C1316CV18 2M x 8 CY7C1916CV18 2M x 9 CY7C1318CV18 1M x 18 CY7C1320CV18 512K x 36

The CY7C1316CV18, CY7C1916CV18, CY7C1318CV18 and CY7C1320CV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input K clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1316CV18 and two 9-bit words in the case of CY7C1916CV18 that burst sequentially into or out of the device. The burst counter always starts with a “0” internally in the case of CY7C1316CV18 and CY7C1916CV18. On CY7C1318CV18 and CY7C1320CV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1318CV18 and two 36-bit words in the case of CY7C1320CV18 sequentially into or out of the device.

Asynchronous inputs include output impedance matching input ZQ . Synchronous data outputs Q, sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks C/C enable maximum system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Maximum Operating Frequency Maximum Operating Current
300 MHz 300 600
278 MHz 278 580
250 MHz 250 550
200 MHz 200 500
167 MHz 167 450

Unit MHz mA

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600

Logic Block Diagram CY7C1316CV18

CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18

A 19:0 20

Address Register

DOFF

CLK Gen.

VREF R/W

NWS[1:0]

Control Logic

Write Reg

Write Reg
1M x 8 Array 1M x 8 Array

Read Data Reg. 16 8

Logic Block Diagram CY7C1916CV18

Write Add. Decode Read Add. Decode

Output

Logic
Ordering Information
“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered”.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
300 CY7C1316CV18-300BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1318CV18-300BZC

CY7C1320CV18-300BZC

CY7C1916CV18-300BZC
300 CY7C1316CV18-300BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free Commercial

CY7C1318CV18-300BZXC

CY7C1320CV18-300BZXC

CY7C1916CV18-300BZXC
300 CY7C1316CV18-300BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1318CV18-300BZI

CY7C1320CV18-300BZI

CY7C1916CV18-300BZI
300 CY7C1316CV18-300BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free Industrial

CY7C1318CV18-300BZXI

CY7C1320CV18-300BZXI

CY7C1916CV18-300BZXI
278 CY7C1316CV18-278BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1318CV18-278BZC

CY7C1320CV18-278BZC

CY7C1916CV18-278BZC
278 CY7C1316CV18-278BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free Commercial

CY7C1318CV18-278BZXC

CY7C1320CV18-278BZXC

CY7C1916CV18-278BZXC
278 CY7C1316CV18-278BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1318CV18-278BZI

CY7C1320CV18-278BZI

CY7C1916CV18-278BZI
278 CY7C1316CV18-278BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free Industrial

CY7C1318CV18-278BZXI

CY7C1320CV18-278BZXI

CY7C1916CV18-278BZXI
250 CY7C1316CV18-250BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm
Ordering Information continued
“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered”.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
250 CY7C1316CV18-250BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1318CV18-250BZI

CY7C1320CV18-250BZI

CY7C1916CV18-250BZI
250 CY7C1316CV18-250BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free Industrial

CY7C1318CV18-250BZXI

CY7C1320CV18-250BZXI

CY7C1916CV18-250BZXI
200 CY7C1316CV18-200BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1318CV18-200BZC

CY7C1320CV18-200BZC

CY7C1916CV18-200BZC
200 CY7C1316CV18-200BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free Commercial

CY7C1318CV18-200BZXC

CY7C1320CV18-200BZXC

CY7C1916CV18-200BZXC
200 CY7C1316CV18-200BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Industrial

CY7C1318CV18-200BZI

CY7C1320CV18-200BZI

CY7C1916CV18-200BZI
200 CY7C1316CV18-200BZXI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free Industrial

CY7C1318CV18-200BZXI

CY7C1320CV18-200BZXI

CY7C1916CV18-200BZXI
167 CY7C1316CV18-167BZC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

Commercial

CY7C1318CV18-167BZC

CY7C1320CV18-167BZC

CY7C1916CV18-167BZC
167 CY7C1316CV18-167BZXC 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm Lead-Free Commercial

CY7C1318CV18-167BZXC

CY7C1320CV18-167BZXC

CY7C1916CV18-167BZXC
167 CY7C1316CV18-167BZI 51-85180 165-ball Fine Pitch Ball Grid Array 13 x 15 x mm

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Datasheet ID: CY7C1318CV18-278BZXC 507957