FDC6322C

FDC6322C Datasheet

FDC6322C Dual N & P Channel , Digital FET

Part	Datasheet
FDC6322C	FDC6322C (pdf)

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November 1997 FDC6322C Dual N & P Channel , Digital FET These dual N & P Channel logic level enhancement mode field effec transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. The device is an improved design especially for low voltage applications as a replacement for bipolar digital transistors in load switching applications. Since bias resistors are not required, this dual digital FET can replace several digital transistors with difference bias resistors. N-Ch 25 V, A, RDS ON = 5 VGS= V. P-Ch 25 V, A, RDS ON = VGS= V. Very low level gate drive requirements allowing direct operation in 3 V circuits. VGS th < V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model Replace NPN & PNP digital transistors. SOT-23 SuperSOTTM-6 Mark: SuperSOTTM-8 SO-8 SOT-223 SOIC-16 Absolute Maximum Ratings TA = 25oC unless other wise noted Symbol Parameter N-Channel VDSS, VCC Drain-Source Voltage, Power Supply Voltage VGSS, VIN Gate-Source Voltage, ID, IO Drain/Output Current - Continuous - Pulsed Maximum Power Dissipation Note 1a Note 1b TJ,TSTG ESD Operating and Storage Tempature Ranger Electrostatic Discharge Rating MIL-STD-883D Human Body Model 100pf / 1500 Ohm THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Note 1a Thermal Resistance, Junction-to-Case Note 1 -55 to 150 140 60 P-Channel -25 -8 -1 Units V A °C kV °C/W °C/W 1997 Fairchild Semiconductor Corporation FDC6322C.Rev B1 DMOS Electrical Characteristics TA = 25 OC unless otherwise noted Parameter Conditions

PDF Datasheet Preview

November 1997

FDC6322C Dual N & P Channel , Digital FET

These dual N & P Channel logic level enhancement mode field effec transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. The device is an improved design especially for low voltage applications as a replacement for bipolar digital transistors in load switching applications. Since bias resistors are not required, this dual digital FET can replace several digital transistors with difference bias resistors.

N-Ch 25 V, A, RDS ON = 5 VGS= V. P-Ch 25 V, A, RDS ON = VGS= V.

Very low level gate drive requirements allowing direct operation in 3 V circuits. VGS th < V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model

Replace NPN & PNP digital transistors.

SOT-23

SuperSOTTM-6 Mark:

SuperSOTTM-8

SO-8

SOT-223

SOIC-16

Absolute Maximum Ratings TA = 25oC unless other wise noted

Symbol Parameter

N-Channel

VDSS, VCC Drain-Source Voltage, Power Supply Voltage

VGSS, VIN Gate-Source Voltage,

ID, IO

Drain/Output Current - Continuous
- Pulsed

Maximum Power Dissipation

Note 1a

Note 1b

TJ,TSTG ESD

Operating and Storage Tempature Ranger

Electrostatic Discharge Rating MIL-STD-883D Human Body Model 100pf / 1500 Ohm

THERMAL CHARACTERISTICS

Thermal Resistance, Junction-to-Ambient Note 1a

Thermal Resistance, Junction-to-Case

Note 1
-55 to 150
140 60

P-Channel -25 -8 -1

Units V A
°C kV
°C/W °C/W
1997 Fairchild Semiconductor Corporation

FDC6322C.Rev B1

DMOS Electrical Characteristics TA = 25 OC unless otherwise noted

Parameter

Conditions

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Datasheet ID: FDC6322C 514074