DM74S374N

DM74S374N Datasheet

DM74S373<br>• DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

Part	Datasheet
DM74S374N	DM74S374N (pdf)

Related Parts	Information
DM74S373N	DM74S373N

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DM74S373 • DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops DM74S373 • DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the DM74S373 are transparent D-type latches meaning that while the enable G is HIGH the Q outputs will follow the data D inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up. The eight flip-flops of the DM74S374 are edge-triggered Dtype flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs. Schmitt-trigger buffered inputs at the enable/clock lines simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output control input can be used to place the eight outputs in either a normal logic state HIGH or LOW logic levels or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF. s Choice of 8 latches or 8 D-type flip-flops in a single package s 3-STATE bus-driving outputs s Full parallel-access for loading s Buffered control inputs s P-N-P input reduce D-C loading on data lines Ordering Code: Order Number Package Number Package Description DM74S373WM M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide DM74S373N N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide DM74S374WM M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide DM74S374N N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams DM74S373N 2000 Fairchild Semiconductor Corporation DS006486 DM74S374N DM74S373 • DM74S374 Truth Tables DM74S373 Output Enable Output Control H = HIGH Level Steady State L = LOW Level Steady State X = Don’t Care Z = High Impedance State = Transition from LOW-to-HIGH level, Q0 = The level of the output before steady-state input conditions were established. Logic Diagrams 74S373 Transparent Latches Output Control DM74S374 Clock Output H L Q0 Z 74S374 Positive-Edge-Triggered Flip-Flops DM74S373 • DM74S374 Absolute Maximum Ratings Note 1 Supply Voltage Input Voltage 5.5V Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DM74S373 Recommended Operating Conditions Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Pulse Width Note 2 Enable HIGH Enable LOW Pulse Width Note 3

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DM74S373
• DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

DM74S373
• DM74S374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the DM74S373 are transparent D-type latches meaning that while the enable G is HIGH the Q outputs will follow the data D inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up.

The eight flip-flops of the DM74S374 are edge-triggered Dtype flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs.

Schmitt-trigger buffered inputs at the enable/clock lines simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output control input can be used to place the eight outputs in either a normal logic state HIGH or LOW logic levels or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF.
s Choice of 8 latches or 8 D-type flip-flops in a single package
s 3-STATE bus-driving outputs s Full parallel-access for loading s Buffered control inputs s P-N-P input reduce D-C loading on data lines
Ordering Code:

Order Number Package Number

Package Description

DM74S373WM

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide

DM74S373N

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

DM74S374WM

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide

DM74S374N

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams

DM74S373N 2000 Fairchild Semiconductor Corporation DS006486

DM74S374N

DM74S373
• DM74S374

Truth Tables

DM74S373

Output

Enable

Output

Control

H = HIGH Level Steady State L = LOW Level Steady State X = Don’t Care Z = High Impedance State = Transition from LOW-to-HIGH level, Q0 = The level of the output before steady-state input conditions were
established.

Logic Diagrams
74S373 Transparent Latches

Output Control

DM74S374

Clock

Output

H L Q0 Z
74S374 Positive-Edge-Triggered Flip-Flops

DM74S373
• DM74S374

Absolute Maximum Ratings Note 1

Supply Voltage

Input Voltage
5.5V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range
−65°C to +150°C

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

DM74S373 Recommended Operating Conditions

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

LOW Level Output Current

Pulse Width Note 2

Enable HIGH

Enable LOW

Pulse Width Note 3

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Datasheet ID: DM74S374N 513845