74LVTH16501MTD

74LVTH16501MTD Datasheet

74LVTH16501 Low Voltage 18-Bit Universal Bus Transceivers with Bushold and 3-STATE Outputs

Part	Datasheet
74LVTH16501MTD	74LVTH16501MTD (pdf)

Related Parts	Information
74LVTH16501MEA	74LVTH16501MEA
74LVTH16501MTDX	74LVTH16501MTDX
74LVTH16501MEAX	74LVTH16501MEAX

PDF Datasheet Preview
74LVTH16501 Low Voltage 18-Bit Universal Bus Transceivers with Bushold and 3-STATE Outputs 74LVTH16501 Low Voltage 18-Bit Universal Bus Transceivers with Bushold and 3-STATE Outputs The LVTH16501 is an 18-bit universal bus transceiver combining D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable OEAB and OEBA , latch-enable LEAB and LEBA , and clock CLKAB and CLKBA inputs. The LVTH16501 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. The transceiver is designed for low voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH16501 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs s Live insertion/extraction permitted s Power up/down high impedance provides glitch-free bus loading s Outputs source/sink −32 mA/+64 mA s Functionally compatible with the 74 series 16501 s ESD Performance: Human-Body Model > 2000V Machine Model > 200V Charged-Device Model > 1000V Ordering Code: Order Number Package Number Package Description 74LVTH16501MEA MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide 74LVTH16501MTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2001 Fairchild Semiconductor Corporation DS500101 74LVTH16501 Connection Diagram Functional Description For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/ flip-flop on the LOW-to-HIGH transition of CLKAB. Outputenable OEAB is active-HIGH. When OEAB is HIGH, the Logic Diagram Pin Descriptions Pin Names Data Register A Inputs/3-STATE Outputs Data Register B Inputs/3-STATE Outputs CLKAB, CLKBA Clock Pulse Inputs LEAB, LEBA Latch Enable Inputs OEAB, OEBA Output Enable Inputs Function Table Note 1 Inputs Output OEAB LEAB CLKAB B0 Note 2 B0 Note 3 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Clock Transition Note 1 A-to-B data flow is shown B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. OEBA is active LOW Note 2 Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. Note 3 Output level before the indicated steady-state input conditions were established. outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A-to-B but uses OEBA, LEBA, and CLKBA. The output enables are complementary OEAB is active-HIGH and OEBA is activeLOW . 74LVTH16501 Absolute Maximum Ratings Note 4 VCC VI VO Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current ICC IGND TSTG DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions

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74LVTH16501 Low Voltage 18-Bit Universal Bus Transceivers with Bushold and 3-STATE Outputs
74LVTH16501 Low Voltage 18-Bit Universal Bus Transceivers with Bushold and 3-STATE Outputs

The LVTH16501 is an 18-bit universal bus transceiver combining D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable OEAB and OEBA , latch-enable LEAB and LEBA , and clock CLKAB and CLKBA inputs.

The LVTH16501 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.

The transceiver is designed for low voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH16501 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.
s Input and output interface capability to systems at 5V VCC
s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs
s Live insertion/extraction permitted s Power up/down high impedance provides glitch-free bus
loading s Outputs source/sink −32 mA/+64 mA s Functionally compatible with the 74 series 16501 s ESD Performance:

Human-Body Model > 2000V Machine Model > 200V Charged-Device Model > 1000V
Ordering Code:

Order Number Package Number

Package Description
74LVTH16501MEA

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide
74LVTH16501MTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2001 Fairchild Semiconductor Corporation DS500101
74LVTH16501

Connection Diagram

Functional Description

For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/ flip-flop on the LOW-to-HIGH transition of CLKAB. Outputenable OEAB is active-HIGH. When OEAB is HIGH, the

Logic Diagram

Pin Descriptions

Pin Names

Data Register A Inputs/3-STATE Outputs

Data Register B Inputs/3-STATE Outputs

CLKAB, CLKBA Clock Pulse Inputs

LEAB, LEBA Latch Enable Inputs

OEAB, OEBA Output Enable Inputs

Function Table Note 1

Inputs

Output

OEAB LEAB CLKAB

B0 Note 2

B0 Note 3

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance
= LOW-to-HIGH Clock Transition

Note 1 A-to-B data flow is shown B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. OEBA is active LOW

Note 2 Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.

Note 3 Output level before the indicated steady-state input conditions were established.
outputs are active. When OEAB is LOW, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A-to-B but uses OEBA, LEBA, and CLKBA. The output enables are complementary OEAB is active-HIGH and OEBA is activeLOW .
74LVTH16501

Absolute Maximum Ratings Note 4

VCC VI VO

Parameter Supply Voltage DC Input Voltage DC Output Voltage

DC Input Diode Current

DC Output Diode Current

DC Output Current

ICC IGND TSTG

DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature

Value

Conditions

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Datasheet ID: 74LVTH16501MTD 513433