AS1328A-BQFT-15

AS1328A-BQFT-15 Datasheet


AS1328

Part Datasheet
AS1328A-BQFT-15 AS1328A-BQFT-15 AS1328A-BQFT-15 (pdf)
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Datasheet

AS1328
3A, 1.5MHz Synchronous DC/DC Step-Down Converter
1 General description

The AS1328 is a high-efficiency, synchronous buck converter that can deliver up to 3A. The device is available in adjustable- and fixedoutput voltage versions. The wide input voltage range 2.7V to 5.5V , automatic Powersave Mode and minimal external component requirements make the AS1328 perfect for any single Li-Ion batterypowered application.

Typical quiescent current with no load is 25uA and decreases to in shutdown mode. The highly efficient duty cycle 100% provides low dropout operation, prolonging battery life in portable systems.

The AS1328 is available with user adjustable output voltage between 0.6V and VIN via an external resistor divider.

The switching frequency 1.5MHz allows the use of a small surface mount inductor. A user adjustable Softstart function limits the input current during start-up. The AS1328 is available in a TQFN 3x3mm 16-pin package. AS1328 offers several power monitoring functions.

Part Name AS1328A AS1328B AS1328C

Description Power-Okay Function Low Battery Detection Power-Okay Function with 215ms delay
2 Key features

Efficiency up to 96% Voltage Range 2.7V to 5.5V Voltage Range factory set 0.7V to 4.8V Output Voltage Range 0.6V to VIN Current 3A battery detection or Power Okay function Frequency Operation 1.5MHz or Powersave Opera-
tion Function Schottky diode required Powersave Operation Dropout Operation 100% Duty Cycle POK timeout optional Quiescent Supply Current 25uA Current protection 3x3mm 16-pin Package.

Figure AS1328 - Typical application diagram

VIN 2.7V to 5.5V

CIN 44uF

VIN SRC

EN POK GND
3 Applications

The device is ideal for mobile communication devices, laptops and PDAs, SSD, point of load supply of uP and FPGA based systems, medical instruments or any other application with high current requirements.

AS1328A
2.2uH SW PGND GND FB RSI

COUT 44uF

VOUT 0.7V to 4.8V, 3A

MODE
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AS1328

Datasheet - Pin assignment
4 Pin assignment

Figure Pin assignment top view of the two versions AS1328A POK function and AS1328B LBI function
16 PVDD 15 VDD 14 FB 13 SRC
16 PVDD 15 VDD 14 FB 13 SRC

PVDD 1 SW 2 SW 3

PGND 4
12 GND AS1328A 11 EN
10 POK Exposed Pad 9 RSI

PVDD 1 SW 2 SW 3

PGND 4
12 GND AS1328B 11 EN
10 LBO Exposed Pad 9 LBI

PGND 5 GND 6 GND 7
The output voltage can be set by an external resistor divider or it is fixed from factory setting. The device is available with a fixed output voltage in 50mV steps from 0.7V up to 2.9V and in 100mV steps from 2.9V to 4.8V see Ordering information on page On the regulated DC voltage an accuracy of 1% is guaranteed for all versions.

Soft start feature is provided by loading pin SRC with an external capacitor Css. For Css higher than 10nF it is possible to increase, proportionally to Css value, the startup time of the device which is limited to 1ms by an inner slewing limitation in the reference voltage. In addition, by forcing pin SRC with less than 500mV bias reference, it is possible to make the output voltage tracking the DC voltage at SRC pin.
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AS1328

Datasheet - Detailed description

Nominal operating duty cycle of the converter, which fixes the output voltage range vs. input voltage, ranges from 15% to For output voltages requiring a duty cycle above 95%, their value can still be obtained by modulating the PMOS on-time as an average result after some cycles at full conduction and others running at 95% duty cycle.

Cycle by cycle peak inductor current limitation max value 4.5A , thermal protection, output over-voltage sensing, UVLO, Enable features are common to all the available variants of the device.

The AS1328 is available in different variants depending on specific features besides the already mentioned external output voltage setting, Power OK POK option and Low battery detection LBI operation can be required for precisely monitoring the regulated output voltage, an external voltage reference or the supply voltage. The AS1328A offers the POK- and the AS1328B offers the LBI-Function. Both functions cannot be offered together.

The AS1328A is available in two variants. In one variant the POK signal is asserted only depending on internal circuitry delay, while in the other version the POK asserts after a 215ms delay. See Power-OK functionality AS1328A only on page 15 for further information.

Main control loop

During normal operation, the internal PMOS power switch is turned on at each rising edge of the system clock, running at 1.5MHz. The SW output of the DC-DC converter gets connected to VIN by means of the power PMOS switch and the current in the coil starts increasing at a rate depending on VIN, the regulated voltage VOUT and the coil. This increase causes the current ripple which is typical in a DC-DC converter. The instantaneous current in the coil oscillates around the average value with a triangular waveform and the ripple is the maximum excursion from this value. Due to the current mode architecture, the current in the PMOS is mirrored a scaled replica is sent to a sense resistor at the input of the PWM comparator where a ramp is generated. Moreover, in order to prevent oscillation at duty cycle larger than 50%, a current ramp, called slope compensation, is added at the same PWM comparator input.

The other input of the PWM comparator is a slow varying signal, resulting from the integration onto the loop filter of error amplifier output. This stage, acting as a transconductor, injects in the loop filter a current proportional to the difference between the regulated output at node FB and an on-chip reference voltage. Eventually a resistor divider, located between the input of the error amplifier and the output regulated voltage at pin FB, sets the desired DC voltage at the load.

Because of the ramping value of the PMOS current, the PWM comparator trips when the drop across the sense resistor gets larger than the slowly varying error amplifier output. This transition turns off the power PMOS and, in turn, it switches on the NMOS after a short delay, to prevent crowbar. The NMOS current starts decreasing at a rate depending on VOUT and the coil size while still being positive because of the continuity from the coil.

NMOS conduction takes place up to a given point, depending on MODE pin value.
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AS1328

Datasheet - Detailed description

Figure Switch voltage and coil current waveforms MODE = high Continuous Operating Mode CCM

Discontinuous Operating Mode DCM

Note Ringing is due to the LC resonant circuit at the load when both PMOS and NMOS are turned off.

In case MODE is logic low see Figure 28 , the process continues up to the next clock cycle. At this event the NMOS is disconnected and a new cycle starts. This means that, in case of light average load and large ripple, the current in the coil may even become negative and the load is temporarily discharged.

Figure Switch voltage and coil current waveforms MODE = low

Note The coil current is allowed to become negative and to discharge the load. The loop operates in negative feedback. When the load current increases, VOUT tends to decrease relative to the nominal value. This causes the error amplifier output voltage to increase, asking for higher peaks in the ramp at the PWM comparator input before terminating the PMOS conduction. This means a current increase from the PMOS that tends to track the load variation. Because of the large gain, the virtual ground at the error amplifier forces the FB node to be a multiple, depending on the voltage divider from FB pin, of the on-chip reference voltage at the other input terminal of the error amplifier.

Powersave Operation MODE = high

Powersave Operation is automatically triggered when MODE signal is high, while it is disabled by forcing MODE as low. When the load current is small, the output capacitor does not need to recover the lost charge at each clock period. Due to the Powersave Operation it is possible to skip some clock cycles. This reduces the power consumption and keeps the efficiency high at any load. Automatic triggering of Powersave Mode is guaranteed by two main facts first, a minimum amount of charge that is injected into the load at each clock cycle second once MODE set at high , it is not allowed to discharge the load by blocking a negative current in the power NMOS.
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AS1328

Datasheet - Detailed description

As a result, if the load current is not high enough to drain all the charge delivered by the PMOS in one clock cycle, the output will tend to diverge. Depending on VIN and VOUT values, this occurs when the load current stays below a value Ith that has an approximate range between 200mA and 600mA. When an internal comparator, whose threshold is set 5% above the nominal value of the output voltage, detects an over-voltage event, the PMOS is immediately shut down. PMOS on-pulses are skipped until the output voltage drops below the over-voltage threshold. In case the load current has not significantly varied in the meantime, the next pulses will bring again the output voltage above the 5% of the threshold. This will initiate a new skip cycle where other PMOS on-pulses cannot be triggered. This sequence, called skip mode, is marked by an oscillation in a very narrow voltage range lying around 5% above the nominal value of VOUT. As soon as the load current increases above the threshold Ith, the skip phase is terminated as the output does no longer diverge and an overvoltage event cannot take place. Anyhow, the skip phase cannot last for a long time even if the load current still remains too low. The system replaces the skip operating mode with the Powersave Mode after a delay typical a few tenth microseconds which depends on the DC-DC converter loop bandwidth and the previous events of the system. In Powersave Mode the clock re-triggers a PMOS pulse only when the output voltage drops below its nominal value, no longer below the 5% of the threshold as previously described. If compared to skip mode, the Powersave Mode prolongs the interval when the DC-DC converter is not dissipating and this time is inversely proportional to the load current.

Figure Typical waveform in Powersave Mode

The cycle in Figure 29 starts with a skip mode whose duration is limited. After a delay the output driver switches to tristate and a restart is triggered after VOUT drops below the nominal value. Successive over_voltage events trigger automatically a powersave cycle, without passing through a skip mode, if the previous one has been terminated very lately. Over_voltage and Out_tristate signals are internal to the device and not available externally.

At clock restart after a powersave cycle, if the load current remains lower than Ith, the output voltage still increases. The over_voltage event puts the system automatically in Powersave Mode without passing through the initial skip mode cycle if the delay between the crossing of the nominal threshold and the over_voltage is less than a given amount.

The Powersave Mode only ends when the load current rises above the threshold and the output is no longer able to diverge. In this operating mode the DC-DC converter dissipates a minimum of energy. The output driver is not charged nor discharged for a long time and most of the analog circuitry is switched off to ensure less than 25uA current dissipation. The benefits over the system efficiency is very large.

Note In powersave mode, the voltage ripple is larger than the one observed in normal operation, as it ranges from the nominal value to 5% in excess at the same time, the ripple frequency is much smaller it is no longer depending on the system clock and it’s mostly determined by the output capacitor value and the load current .

Fixed Frequency Operation MODE = low

If the pin MODE is pulled to logic low, the Powersave Mode is disabled. In this operation mode the NMOS and the PMOS are always complementarily switching on and off, accordingly to the relationship D = VOUT / VIN, where D is the duty cycle of the on-pulses of the PMOS. As the minimum allowed duty cycle D is less than the minimum VOUT / VIN according to the typical operation conditions , it is not possible that the output can diverge.
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AS1328

Datasheet - Detailed description

The possibility of driving also a negative current through the NMOS drains the residual charge coming from the minimum PMOS on-pulses that the load current cannot eventually remove. With mode low, the output rises above 5% of the threshold only in case of a large variation in the load current. Hence, unlike Powersave Mode, the skip mode is still present to avoid large overshoot which could lower the reliability. The PMOS is off for all the time, the output stays above 5% of the threshold and the NMOS is not allowed to discharge with a negative current. By avoiding the integration of negative currents in the coil, which might be large in module, this solution shows good damping properties and a smooth recovery for the output voltage.

Short-circuit protection
For the fixed output voltage available from 0.7V to 4.8V, see Ordering information on page 29 connect pin FB to VOUT see Figure

Figure AS1328 - Fixed Output Version

VIN 2.7V to 5.5V

CIN 44uF
2.2uH

VOUT

COUT
0.7V to 4.8V
44uF

PGND

AS1328A

MODE

Adjustable Output Voltage

For the adjustable output voltage version connect a voltage divider to pin FB see Figure The voltage divider from VOUT to GND programs the output voltage from 0.6V to VIN via pin FB as:

VOUT = 0.6V 1 + R1/R2

Figure AS1328 - External net for the Adjustable Output Version
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AS1328

Datasheet - Application information

The upper terminal of resistor R1 must be connected directly to the load capacitor positive terminal, while the lower terminal for R2 must be connected the signal ground GND. About R1 and R2 resistor values, the upper limits come from the leakage current at FB pin. Usually values less than 1MW provide accurate enough solutions.

In addition, thinking of the stability of the system, it is welcome to add a capacitor CF in parallel to R1. This improves the phase margin and improves load transient performances by bringing the output spike from the load to FB pin without any significant attenuation.

In order to accomplish this, it is welcome to have R2*CF time constant inside the gain bandwidth of the device. Usually the choice R2*CF = 100ms is sufficient. Higher values should be carefully evaluated as the settling time will be limited by the time constant R1*CF. In case R1/R2 is quite large i.e. large VOUT values , the settling may become longer than the one foreseen by the internal soft start circuitry. Of course this limit can be remarkably relaxed in case an external soft start capacitor Css is used.

Soft start capacitor selection CSS

The SRC pin is capable of sourcing a pull-up current of 4uA. Until the voltage does not reach 600mV, SRC provides the reference voltage to startup the DC-DC converter.

A nominal 1ms startup time structure is implemented on-chip, hence capacitors lower than 4uA*1ms/0.6V = 6.7nF are not effective in changing the startup time of the device.

Higher values for CSS will determine a soft start time tSS for the DC-DC converter as follows:
tSS = 0.6V*CSS/4uA
under the assumption tSS>>1ms.

For example a CSS of 100nF would make nearly 15ms as soft start time.

As an alternative to the capacitor CSS, a voltage source VSRC can be used to force the SRC pin. Two constraints must be considered to ensure accuracy must be able to drain 4uA nominal current start-up, VSRC must stop at a higher voltage than 0.6V, to not affecting the steady state value a suggested safety margin is to set-
tle VSRC above 1V.

Note In case VSRC steady state value is below 450mV, it is possible to have a scaled down version of the output voltage VSRC/0.6 smaller than the nominal value .
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AS1328

Datasheet - Application information

External component selection

Inductor selection

The choice for the coil must take into account several and sometimes contradictory requirements.

Usually the selection suggests small values for the following reasons 1 improved load transient response a larger coil is less prone to change its current 2 efficiency at heavy loads the series parasitic of the coil directly contributes to power dissipation depending on iL2. As a larger coil value means more turns of wire and hence a larger series parasitic, a small value for L is welcome when efficiency is a key parameter 3 stability and jitter in a current mode DC-DC converter, stability is ensured with large margins because the replica of the ramping current in the power PMOS is sent to the input of the PWM comparator. A smaller slope, i.e. a larger coil, makes the switching time of the comparator more sensitive to noise. In this way the duty cycle would suffer from jitter. To make matter worse, if the coil is large, the replica of the ramping current becomes quite smaller than the slope compensation ramp and the system tends to behave like a voltage mode converter where stability constraints are usually stricter and the device may oscillate.

Anyhow it is not possible to ignore those following reasons which recommend a larger coil value.

Peak current limitation The positive current ripple brings the PMOS current temporarily higher than the average one. Care must be taken not to reach the over-current limit. If a large ripple is accepted, larger margins must be taken between the maximum DC load current IOUTMAX and the over-current threshold IOVERCURRENT as follows.
Ordering Marking
last two digits of the current year

WW manufacturing week

Q plant identifier

ZZ free choice / traceability code
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AS1328

Datasheet - Package drawings and markings

Figure TQFN 3x3mm 16-pin Package
27 - 30

AS1328

Datasheet - Package drawings and markings

Date 30th Oct., 2012 29th May, 2013

Owner crc tka

Description Updated Absolute Maximum Ratings Updated Absolute Maximum Ratings
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AS1328

Datasheet
11 Ordering information

The device is available as the standard products listed in Table
Table Ordering Information
Ordering Code

Marking

AS1328A-BQFT-AD ASQ3

AS1328A-BQFT-12

ASQ4

AS1328A-BQFT-15

ASQ5

AS1328A-BQFT-18

ASQ6

AS1328B-BQFT-AD

ASS4

AS1328B-BQFT-12

ASS5

AS1328B-BQFT-15

ASS6

AS1328B-BQFT-18

ASS7

AS1328C-BQFT-AD

ASS8

Output
3A, 1.5MHz Synchronous DC/ adjustable DC Step-Down Converter,

POK function version
1.2V
3A, 1.5MHz Synchronous DC/ DC Step-Down Converter,

POK function version
1.5V
3A, 1.5MHz Synchronous DC/ DC Step-Down Converter,

POK function version
1.8V
3A, 1.5MHz Synchronous DC/ DC Step-Down Converter,

POK function version
3A, 1.5MHz Synchronous DC/ adjustable DC Step-Down Converter,

LBI function version
1.2V
3A, 1.5MHz Synchronous DC/ DC Step-Down Converter,

LBI function version
1.5V
3A, 1.5MHz Synchronous DC/ DC Step-Down Converter,

LBI function version
1.8V
3A, 1.5MHz Synchronous DC/ DC Step-Down Converter,
Datasheet - Ordering information

Copyrights

Copyright 1997-2012, ams AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies.

Disclaimer

Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by ams AG is believed to be correct and accurate. However, ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.

Contact Information

Headquarters ams AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel +43 0 3136 500 0 Fax +43 0 3136 525 01

For Sales Offices, Distributors and Representatives, please visit:
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Datasheet ID: AS1328A-BQFT-15 519591