DM74S174N

DM74S174N Datasheet

DM74S174<br>• DM74S175 Hex/Quad D Flip-Flop with Clear

Part	Datasheet
DM74S174N	DM74S174N (pdf)

Related Parts	Information
DM74S175N	DM74S175N

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DM74S174 • DM74S175 Hex/Quad D Flip-Flop with Clear DM74S174 • DM74S175 Hex/Quad D Flip-Flop with Clear These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad DM74S175 versions feature complementary outputs from each flip-flop. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output. s DM74S174 contain six flip-flops with single-rail outputs. s DM74S175 contain four flip-flops with double-rail out- puts. s Buffered clock and direct clear inputs s Individual data input to each flip-flop s Applications include: Buffer/storage registers Shift registers Pattern generators s Typical clock frequency 110 MHz s Typical power dissipation per flip-flop 75mW Ordering Code: Order Number DM74S174N DM74S175N Package Number Package Description N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Connection Diagrams DM74S174 DM74S175 2000 Fairchild Semiconductor Corporation DS006472 DM74S174 • DM74S175 Function Table Each Flip-Flop Inputs Clear Clock H = HIGH Level steady state L = LOW Level steady state X = Don’t Care = Transition from LOW-to-HIGH level Q0 = The level of Q before the indicated steady-state input conditions were established. Note 1 DM74S175 only. Logic Diagrams DM74S174 Outputs Q Note 1 DM74S175 DM74S174 • DM74S175 Absolute Maximum Ratings Note 2 Supply Voltage Input Voltage 5.5V Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Note 2 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current fCLK

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DM74S174
• DM74S175 Hex/Quad D Flip-Flop with Clear

DM74S174
• DM74S175 Hex/Quad D Flip-Flop with Clear

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad DM74S175 versions feature complementary outputs from each flip-flop.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output.
s DM74S174 contain six flip-flops with single-rail outputs. s DM74S175 contain four flip-flops with double-rail out-
puts. s Buffered clock and direct clear inputs s Individual data input to each flip-flop s Applications include:

Buffer/storage registers Shift registers Pattern generators s Typical clock frequency 110 MHz s Typical power dissipation per flip-flop 75mW
Ordering Code:

Order Number DM74S174N DM74S175N

Package Number

Package Description

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

Connection Diagrams

DM74S174

DM74S175
2000 Fairchild Semiconductor Corporation DS006472

DM74S174
• DM74S175

Function Table Each Flip-Flop

Inputs

Clear

Clock

H = HIGH Level steady state L = LOW Level steady state X = Don’t Care = Transition from LOW-to-HIGH level Q0 = The level of Q before the indicated steady-state input conditions were established.

Note 1 DM74S175 only.

Logic Diagrams

DM74S174

Outputs

Q Note 1

DM74S175

DM74S174
• DM74S175

Absolute Maximum Ratings Note 2

Supply Voltage

Input Voltage
5.5V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range
−65°C to +150°C

Note 2 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

LOW Level Output Current
fCLK

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Datasheet ID: DM74S174N 513834