DM74S138N

DM74S138N Datasheet

DM74S138<br>• DM74S139 Decoder/Demultiplexer

Part	Datasheet
DM74S138N	DM74S138N (pdf)

Related Parts	Information
DM74S139N	DM74S139N

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DM74S138 • DM74S139 Decoder/Demultiplexer DM74S138 • DM74S139 Decoder/Demultiplexer These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The DM74S138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable inputs. Two active-LOW and one active-HIGH enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The DM74S139 comprises two separate two-line-to-fourline decoders in a single package. The active-LOW enable input can be used as a data line in demultiplexing applications. All of these decoders/demultiplexers feature fully buffered inputs, presenting only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design. s Designed specifically for high speed Memory decoders Data transmission systems s DM74S138 3-to-8-line decoders incorporates 3 enable inputs to simplify cascading and/or data reception s DM74S139 contains two fully independent 2-to-4-line decoders/demultiplexers s Schottky clamped for high performance s Typical propagation delay time 3 levels of logic DM74S138 8 ns DM74S139 ns s Typical power dissipation DM74S138 245 mW DM74S139 300 mW Ordering Code: Order Number DM74S138N DM74S139N Package Number Package Description N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 2000 Fairchild Semiconductor Corporation DS006466 DM74S138 • DM74S139 Connection Diagrams DM74S138 DM74S139 Function Tables DM74S138 DM74S139 Inputs Enable Select Outputs Inputs Enable Select Outputs G1 G2* C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 B A Y0 Y1 Y2 Y3 X H XXX H L X XXX H H L LLL L H H L LLH H L H H L LHL H L H H L LHH H L H H L HLL H L H H L HLH H L H L HH L H L H * G2 = G2A + G2B H = HIGH level H L H L = LOW level X = don’t care either LOW or HIGH logic level Logic Diagrams DM74S138 DM74S139 DM74S138 • DM74S139 Absolute Maximum Ratings Note 1

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DM74S138
• DM74S139 Decoder/Demultiplexer

DM74S138
• DM74S139 Decoder/Demultiplexer

These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The DM74S138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable inputs. Two active-LOW and one active-HIGH enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

The DM74S139 comprises two separate two-line-to-fourline decoders in a single package. The active-LOW enable input can be used as a data line in demultiplexing applications.

All of these decoders/demultiplexers feature fully buffered inputs, presenting only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design.
s Designed specifically for high speed Memory decoders Data transmission systems
s DM74S138 3-to-8-line decoders incorporates 3 enable inputs to simplify cascading and/or data reception
s DM74S139 contains two fully independent 2-to-4-line decoders/demultiplexers
s Schottky clamped for high performance s Typical propagation delay time 3 levels of logic

DM74S138 8 ns DM74S139 ns s Typical power dissipation DM74S138 245 mW DM74S139 300 mW
Ordering Code:

Order Number DM74S138N DM74S139N

Package Number

Package Description

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
2000 Fairchild Semiconductor Corporation DS006466

DM74S138
• DM74S139

Connection Diagrams

DM74S138

DM74S139

Function Tables

DM74S138

DM74S139

Inputs Enable Select

Outputs

Inputs

Enable

Select

Outputs

G1 G2* C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

B A Y0 Y1 Y2 Y3

X H XXX H

L X XXX H

H L LLL L H

H L LLH H L H

H L LHL H L H

H L LHH H L H

H L HLL H L H

H L HLH H L H

L HH L H L H
* G2 = G2A + G2B H = HIGH level

H L H L = LOW level

X = don’t care either LOW or HIGH logic level

Logic Diagrams

DM74S138

DM74S139

DM74S138
• DM74S139

Absolute Maximum Ratings Note 1

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Datasheet ID: DM74S138N 513827