DM74LS191N

DM74LS191N Datasheet

DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control

Part	Datasheet
DM74LS191N	DM74LS191N (pdf)

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DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control The outputs of the four master-slave flip-flops are triggered on a LOW-to-HIGH level transition of the clock input, if the enable input is LOW. A HIGH at the enable input inhibits counting. Level changes at either the enable input or the down/up input should be made only when the clock input is HIGH. The direction of the count is determined by the level of the down/up input. When LOW, the counter counts up and when HIGH, it counts down. The counter is fully programmable that is, the outputs may be preset to either level by placing a LOW on the load input and entering the desired data at the data inputs. The output will change independent of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. The clock, down/up, and load inputs are buffered to lower the drive requirement which significantly reduces the number of clock drivers, etc., required for long parallel words. Two outputs have been made available to perform the cascading function ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock when the counter overflows or underflows. The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the clock input when an overflow or underflow condition exists. The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count output can be used to accomplish look-ahead for high-speed operation. s Counts binary s Single down/up count control line s Count enable control input s Ripple clock output for cascading s Asynchronously presettable with load control s Parallel outputs s Cascadable for n-bit applications s Average propagation delay 20 ns s Typical clock frequency 25 MHz s Typical power dissipation 100 mW Ordering Code: Order Number Package Number Package Description DM74LS191M M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body DM74LS191N N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 1999 Fairchild Semiconductor Corporation DS006405.prf DM74LS191 Connection Diagram Timing Diagram DM74LS191 Logic Diagram Pin 16 = VCC, Pin 8 = GND DM74LS191 Absolute Maximum Ratings Note 1 Storage Temperature Range Input Voltage Operating Free Air Temp. Range Supply Voltage −65°C to +150°C 7V 0°C to +70°C 7V Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current fCLK Clock Frequency Note 2 Pulse Width Note 2 Data Setup Time Note 2 Data Hold Time Note 2 Enable Time to Clock Note 2 Free Air Operating Temperature Note 2 TA = 25°C and VCC = 5V. Min Nom Clock Load DC Electrical Characteristics Parameter Conditions Input Clamp Voltage HIGH Level Output VCC = Min, II = − 18 mA VCC = Min, IOH = Max Voltage VIL = Max, VIH = Min

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DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control

DM74LS191 Synchronous 4-Bit Up/Down Counter with Mode Control

The outputs of the four master-slave flip-flops are triggered on a LOW-to-HIGH level transition of the clock input, if the enable input is LOW. A HIGH at the enable input inhibits counting. Level changes at either the enable input or the down/up input should be made only when the clock input is HIGH. The direction of the count is determined by the level of the down/up input. When LOW, the counter counts up and when HIGH, it counts down.

The counter is fully programmable that is, the outputs may be preset to either level by placing a LOW on the load input and entering the desired data at the data inputs. The output will change independent of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs.

The clock, down/up, and load inputs are buffered to lower the drive requirement which significantly reduces the number of clock drivers, etc., required for long parallel words.

Two outputs have been made available to perform the cascading function ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock when the counter overflows or underflows. The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the clock input when an overflow or underflow condition exists. The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count output can be used to accomplish look-ahead for high-speed operation.
s Counts binary s Single down/up count control line s Count enable control input s Ripple clock output for cascading s Asynchronously presettable with load control s Parallel outputs s Cascadable for n-bit applications s Average propagation delay 20 ns s Typical clock frequency 25 MHz
s Typical power dissipation 100 mW
Ordering Code:

Order Number Package Number

Package Description

DM74LS191M

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Body

DM74LS191N

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
1999 Fairchild Semiconductor Corporation DS006405.prf

DM74LS191

Connection Diagram

Timing Diagram

DM74LS191

Logic Diagram

Pin 16 = VCC, Pin 8 = GND

DM74LS191

Absolute Maximum Ratings Note 1

Storage Temperature Range Input Voltage Operating Free Air Temp. Range Supply Voltage
−65°C to +150°C 7V
0°C to +70°C 7V

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

LOW Level Output Current
fCLK

Clock Frequency Note 2

Pulse Width

Note 2

Data Setup Time Note 2

Data Hold Time Note 2

Enable Time to Clock Note 2

Free Air Operating Temperature

Note 2 TA = 25°C and VCC = 5V.

Min Nom

Clock

Load

DC Electrical Characteristics

Parameter

Conditions

Input Clamp Voltage

HIGH Level Output

VCC = Min, II = − 18 mA VCC = Min, IOH = Max

Voltage

VIL = Max, VIH = Min

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Datasheet ID: DM74LS191N 513776