DM74LS112AN

DM74LS112AN Datasheet

DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

Part	Datasheet
DM74LS112AN	DM74LS112AN (pdf)

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DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse. Data on the J and K inputs may be changed while the clock is HIGH or LOW without affecting the outputs as long as the setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Ordering Code: Order Number Package Number Package Description DM74KS112AM M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow DM74LS112AN N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs PR CLR CLK J K LHXXX HL XXX L X H Note 1 H Note 1 HH H L Toggle HHHX X H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level = Negative Going Edge of Pulse Q0 = The output logic level before the indicated input conditions were established. Toggle = Each output changes to the complement of its previous level on each falling edge of the clock pulse. Note 1 This configuration is nonstable that is, it will not persist when preset and/or clear inputs return to their inactive HIGH level. 2000 Fairchild Semiconductor Corporation DS006382 DM74LS112A Absolute Maximum Ratings Note 2 Supply Voltage Input Voltage Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Note 2 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current fCLK Clock Frequency Note 3 fCLK Clock Frequency Note 5 Pulse Width Clock HIGH Note 3 Preset LOW 0 20 25

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DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

DM74LS112A

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse. Data on the J and K inputs may be changed while the clock is HIGH or LOW without affecting the outputs as long as the setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.
Ordering Code:

Order Number Package Number

Package Description

DM74KS112AM

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

DM74LS112AN

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

Outputs

PR CLR CLK J K

LHXXX

HL XXX

L X H Note 1 H Note 1

HH H L

Toggle

HHHX X

H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level = Negative Going Edge of Pulse Q0 = The output logic level before the indicated input conditions were
established. Toggle = Each output changes to the complement of its previous level on
each falling edge of the clock pulse.

Note 1 This configuration is nonstable that is, it will not persist when preset and/or clear inputs return to their inactive HIGH level.
2000 Fairchild Semiconductor Corporation DS006382

DM74LS112A

Absolute Maximum Ratings Note 2

Supply Voltage

Input Voltage

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range
−65°C to +150°C

Note 2 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

LOW Level Output Current
fCLK

Clock Frequency Note 3
fCLK

Clock Frequency Note 5

Pulse Width

Clock HIGH

Note 3

Preset LOW
0 20 25

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Datasheet ID: DM74LS112AN 513757