DM74AS874WM

DM74AS874WM Datasheet

DM74AS874 Dual 4-Bit D-Type Edge-Triggered Flip-Flop

Part	Datasheet
DM74AS874WM	DM74AS874WM (pdf)

Related Parts	Information
DM74AS874WMX	DM74AS874WMX
DM74AS874NT	DM74AS874NT

PDF Datasheet Preview
DM74AS874 Dual 4-Bit D-Type Edge-Triggered Flip-Flop DM74AS874 Dual 4-Bit D-Type Edge-Triggered Flip-Flop These dual 4-bit inverting registers feature totem-pole 3STATE outputs designed specifically for driving highlycapacitive or relatively low-impedance loads. The highimpedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the DM74AS874 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs. A buffered output control input can be used to place the eight outputs in either a normal logic state HIGH or LOW logic levels or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF. The pinout is arranged to ease printed circuit board layout. All data inputs are on one side of the package, while all outputs are on the other side. s Switching specifications at 50 pF s Switching specifications guaranteed over full tempera- ture and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s 3-STATE buffer-type outputs drive bus lines directly s Space saving 300 mil wide package s Bus structured pinout Ordering Code: Order Number Package Number Package Description DM74AS874WM M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide DM74AS874NT N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram 2003 Fairchild Semiconductor Corporation DS006331 DM74AS874 Function Table Inputs L = LOW State H = HIGH State X = Don’t Care = Positive Edge Transition Z = High Impedance State Q0 = Previous Condition of Q CLK X L Output Logic Diagram DM74AS874 Absolute Maximum Ratings Note 1 Supply Voltage Input Voltage Voltage Applied to Disabled Output 5.5V Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Typical N Package 47.0°C/W Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current fCLK Clock Frequency tWCLK Width of Clock Pulse HIGH tWCLR tSU Width of Clear Pulse Setup Time Data Note 2 Clear Inactive Data Hold Time Note 2

PDF Datasheet Preview

DM74AS874 Dual 4-Bit D-Type Edge-Triggered Flip-Flop

DM74AS874 Dual 4-Bit D-Type Edge-Triggered Flip-Flop

These dual 4-bit inverting registers feature totem-pole 3STATE outputs designed specifically for driving highlycapacitive or relatively low-impedance loads. The highimpedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight flip-flops of the DM74AS874 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs.

A buffered output control input can be used to place the eight outputs in either a normal logic state HIGH or LOW logic levels or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of the flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF.

The pinout is arranged to ease printed circuit board layout. All data inputs are on one side of the package, while all outputs are on the other side.
s Switching specifications at 50 pF s Switching specifications guaranteed over full tempera-
ture and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL
process s 3-STATE buffer-type outputs drive bus lines directly s Space saving 300 mil wide package s Bus structured pinout
Ordering Code:

Order Number Package Number

Package Description

DM74AS874WM

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide

DM74AS874NT

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram
2003 Fairchild Semiconductor Corporation DS006331

DM74AS874

Function Table

Inputs

L = LOW State H = HIGH State X = Don’t Care = Positive Edge Transition Z = High Impedance State Q0 = Previous Condition of Q

CLK X L

Output

Logic Diagram

DM74AS874

Absolute Maximum Ratings Note 1

Supply Voltage

Input Voltage

Voltage Applied to Disabled Output
5.5V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range
−65°C to +150°C

Typical N Package
47.0°C/W

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

LOW Level Output Current
fCLK

Clock Frequency
tWCLK

Width of Clock Pulse

HIGH
tWCLR tSU

Width of Clear Pulse

Setup Time

Data

Note 2

Clear Inactive

Data Hold Time Note 2

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Datasheet ID: DM74AS874WM 513745