DM74AS873NT

DM74AS873NT Datasheet

DM74AS873 Dual 4-Bit D-Type Transparent Latches with 3-STATE Outputs

Part	Datasheet
DM74AS873NT	DM74AS873NT (pdf)

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DM74AS873 Dual 4-Bit D-Type Transparent Latches with 3-STATE Outputs DM74AS873 Dual 4-Bit D-Type Transparent Latches with 3-STATE Outputs These dual 4-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches of the DM74AS873 are transparent Dtype latches meaning that while the enable G is HIGH the Q outputs will follow the data D inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up. A buffered output control input can be used to place the eight outputs in either a normal logic state HIGH or LOW logic levels or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. The output control does not affect the internal operation of the latches. That is, the old data can be retained or new data can be entered even while the outputs are OFF. The pinout is arranged to ease printed circuit board layout. All data inputs are on one side of the package while all outputs are on the other side. s Switching specifications at 50 pF s Switching specifications guaranteed over full tempera- ture and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s 3-STATE buffer-type outputs drive bus lines directly s Space Saving 300 Mil Wide Package s Bus structured pinout Ordering Code: Order Number Package Number Package Description DM74AS873NT N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram 2003 Fairchild Semiconductor Corporation DS006330 DM74AS873 Function Table Inputs L = LOW State H = HIGH State X = Don’t Care Z = High Impedance State Q0 = Previous Condition of Q Output Logic Diagram DM74AS873 Absolute Maximum Ratings Note 1 Supply Voltage Input Voltage Applied to Disabled Output Operating Free Air Temperature Range Storage Temperature Range Typical N Package 7V 5.5V 0°C to +70°C −65°C to +150°C 47.0°C/W Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Pulse Width Enable HIGH Clear LOW Data Setup Time Note 2 Data Hold Time Note 2 Free Air Operating Temperature Note 2 The arrow indicates the negative edge of the enable is used for reference. Nom 5 Units −15 Electrical Characteristics over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C. Parameter Conditions Input Clamp Voltage HIGH Level Output Voltage LOW Level

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DM74AS873 Dual 4-Bit D-Type Transparent Latches with 3-STATE Outputs

DM74AS873 Dual 4-Bit D-Type Transparent Latches with 3-STATE Outputs

These dual 4-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the DM74AS873 are transparent Dtype latches meaning that while the enable G is HIGH the Q outputs will follow the data D inputs. When the enable is taken LOW the output will be latched at the level of the data that was set up.

A buffered output control input can be used to place the eight outputs in either a normal logic state HIGH or LOW logic levels or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of the latches. That is, the old data can be retained or new data can be entered even while the outputs are OFF.

The pinout is arranged to ease printed circuit board layout. All data inputs are on one side of the package while all outputs are on the other side.
s Switching specifications at 50 pF s Switching specifications guaranteed over full tempera-
ture and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL
process s 3-STATE buffer-type outputs drive bus lines directly s Space Saving 300 Mil Wide Package s Bus structured pinout
Ordering Code:

Order Number Package Number

Package Description

DM74AS873NT

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram
2003 Fairchild Semiconductor Corporation DS006330

DM74AS873

Function Table

Inputs

L = LOW State H = HIGH State X = Don’t Care Z = High Impedance State Q0 = Previous Condition of Q

Output

Logic Diagram

DM74AS873

Absolute Maximum Ratings Note 1

Supply Voltage Input Voltage Applied to Disabled Output Operating Free Air Temperature Range Storage Temperature Range Typical

N Package
7V 5.5V 0°C to +70°C −65°C to +150°C
47.0°C/W

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

LOW Level Output Current

Pulse Width

Enable HIGH

Clear LOW

Data Setup Time Note 2

Data Hold Time Note 2

Free Air Operating Temperature

Note 2 The arrow indicates the negative edge of the enable is used for reference.

Nom 5

Units
−15

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C.

Parameter

Conditions

Input Clamp Voltage

HIGH Level

Output Voltage

LOW Level

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Datasheet ID: DM74AS873NT 513744