DM74AS74SJ

DM74AS74SJ Datasheet


DM74AS74 Dual D-Type Positive-Edge-Triggered Flip-Flop with Preset and Clear

Part Datasheet
DM74AS74SJ DM74AS74SJ DM74AS74SJ (pdf)
Related Parts Information
DM74AS74MX DM74AS74MX DM74AS74MX
DM74AS74M DM74AS74M DM74AS74M
DM74AS74SJX DM74AS74SJX DM74AS74SJX
DM74AS74N DM74AS74N DM74AS74N
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DM74AS74 Dual D-Type Positive-Edge-Triggered Flip-Flop with Preset and Clear

DM74AS74 Dual D-Type Positive-Edge-Triggered Flip-Flop with Preset and Clear

The AS74 is a dual edge-triggered flip-flops. Each flip-flop has individual D, clock, clear and preset inputs, and also complementary Q and Q outputs.

Information at input D is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect.

Asynchronous preset and clear inputs will set or clear Q output respectively upon the application of LOW level signal.
s Switching specifications at 50 pF s Switching specifications guaranteed over full tempera-
ture and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL
process s Functionally and pin-for-pin compatible with Schottky
and LS TTL counterpart s Improved AC performance over S74 at approximately
half the power
Ordering Code:

Order Number Package Number

Package Description

DM74AS74M

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

DM74AS74SJX

M14D
14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide

DM74AS74N

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

Outputs

PR CLR CLK D

LHXX

HLXX

L X H Note 1 H Note 1

HHL X

L = LOW State H = HIGH State X = Don't Care = Positive Edge Transition Q0 = Previous Condition of Q

Note 1 This condition is nonstable it will not persist when preset and clear inputs return to their inactive HIGH level. The output levels in this condition are not guaranteed to meet the VOH specification.
2000 Fairchild Semiconductor Corporation DS006282

DM74AS74

Logic Diagram

DM74AS74

Absolute Maximum Ratings Note 2

Supply Voltage

Input Voltage

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range
−65°C to +150°C

Typical N Package
76.0°C/W

M Package
107.0°C/W

Note 2 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

LOW Level Output Current
fCLK

Clock Frequency
tW CLK

Width of Clock Pulse

HIGH

Pulse Width Preset & Clear LOW

Data Setup Time Note 3
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Datasheet ID: DM74AS74SJ 513740