FIN1049MTC
FIN1049MTC Datasheet
FIN1049 LVDS Dual Line Driver with Dual Line Receiver
| Part | Datasheet |
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FIN1049MTC |
FIN1049MTC (pdf) |
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| FIN1049 LVDS Dual Line Driver with Dual Line Receiver FIN1049 LVDS Dual Line Driver with Dual Line Receiver This dual Driver-Receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling LVDS technology. The Driver accepts LVTTL inputs and translates them to LVDS outputs. The Receiver accepts LVDS inputs and translates them to LVTTL outputs. The LVDS levels have a typical differential output swing of 350mV which provide for low EMI at ultra low power dissipation even at high frequencies. The FIN1049 can accept LVPECL inputs for translating from LVPECL to LVDS. The En and Enb inputs are ANDed together to enable/disable the outputs. The enables are common to all four outputs. A single line driver and single line receiver function is also available in the FIN1019. s Greater than 400 Mbps data rate s 3.3V power supply operation s Low power dissipation s Fail safe protection for open-circuit conditions s Meets or exceeds the TIA/EIA-644-A LVDS standard s 16-pin TSSOP package saves space s Flow-through pinout simplifies PCB layout s Enable/Disable for all outputs s Industrial operating temperature range: −40°C to +85°C Ordering Code: Order Number Package Number Package Description FIN1049MTC MTC16 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Pin Descriptions Connection Diagram Pin Name RIN1+, RIN2+ Non-Inverting LVDS Inputs RIN1−, RIN2− Inverting LVDS Inputs DOUT1+, DOUT2+ Non-Inverting Driver Outputs DOUT1−, DOUT2− Inverting Driver Outputs EN, ENb Driver Enable Pins for All Outputs ROUT1, ROUT2 DIN2, DIN2 VCC GND LVTTL Output Pins for ROUT1 and ROUT2 LVTTL Input Pins for DIN1 and DIN2 Power Supply 3.3V Ground 2003 Fairchild Semiconductor Corporation DS500846 FIN1049 Function Table Inputs Outputs LVTTL ROUT1 ROUT2 H = HIGH Logic Level L = LOW Logic Level or OPEN X = Don’t Care Z = High Impedance Note 1 Any unused Receiver Inputs should be left Open. Inputs LVDS Note 1 RIN#+ RIN#− Open Current Fail Safe Condition Outputs LVDS DOUT#+ DOUT#− Functional Diagram FIN1049 Absolute Maximum Ratings Note 2 Supply Voltage VCC LVDS DC Input Voltage VIN LVDS DC Output Voltage VOUT Driver Short Circuit Current IOSD Storage Temperature Range TSTG Max Junction Temperature TJ Lead Temperature TL Soldering, 10 seconds ESD Human Body Model ESD Machine Model −0.5V to +4.6V −0.5V to +4.6V −0.5V to +4.6V Continuous 10mA −65°C to +150°C 150°C 260°C >7000V >250V Recommended Operating Conditions Supply Voltage VCC Magnitude of Differential Voltage |VID| Operating Temperature TA 3.0V to 3.6V 100mV to VCC −40°C to +85°C Note 2 The “Absolute Maximum Ratings” are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specification. |
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