DM74AS648WM

DM74AS648WM Datasheet

DM74AS646<br>• DM74AS648 Octal Bus Transceiver and Register

Part	Datasheet
DM74AS648WM	DM74AS648WM (pdf)

Related Parts	Information
DM74AS648NT	DM74AS648NT
DM74AS646WM	DM74AS646WM
DM74AS646NT	DM74AS646NT
DM74AS646WMX	DM74AS646WMX
DM74AS648WMX	DM74AS648WMX

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DM74AS646 • DM74AS648 Octal Bus Transceiver and Register DM74AS646 • DM74AS648 Octal Bus Transceiver and Register This device incorporates an octal bus transceiver and an octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to bus. This bus transceiver features totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide this device with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. It is particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The registers in the DM74AS646, DM74AS648 are edgetriggered D-type flip-flops. On the positive transition of the clock CAB or CBA , the input bus data is stored. The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred. A LOW input level selects real-time data, and a HIGH level selects stored data. The select controls have a “make before break” configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between stored and real-time data. The enable G and direction control pins provide four modes of operation real-time data transfer from bus A to B, realtime data transfer from bus B to A, real-time bus A and/or B data transfer to internal storage, or internal store data transfer to bus A or B. When the enable G pin is LOW, the direction pin selects which bus receives data. When the enable G pin is HIGH, both buses become disabled yet their input function is still enabled. s Switching specifications at 50 pF s Switching specifications guaranteed over full tempera- ture and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s Functionally and pin-for-pin compatible with LS TTL counterpart s 3-STATE buffer-type outputs drive bus lines directly Ordering Code: Order Number Package Number Package Description DM74AS646WM M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide DM74AS646NT N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide DM74AS648WM M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide DM74AS648NT N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2003 Fairchild Semiconductor Corporation DS006324 DM74AS646 • DM74AS648 Connection Diagram Function Table Inputs Data I/O Note 1 Operation or Function G DIR CAB CBA SAB SBA A1 thru A8 B1 thru B8 DM74AS646 H X H or L H or L X Input Input Isolation, Hold Storage Store A and B Data DM74AS648 Isolation, Hold Storage Store A and B Data X H or L X H Output Input Real Time B Data to A Bus Real Time B Data to A Bus Stored B Data to A Bus Stored B Data to A Bus Input Output Real Time A Data to B Bus Real Time A Data to B Bus H or L X H X Stored A Data to B Bus Stored A Data to B Bus Input Unspecified Store A, B Unspecified Store A, B Unspecified Note 1 Note 1 Note 1 X Unspecified Input Store B, A Unspecified Store B, A Unspecified Note 1 Note 1 Note 1 level transition Note 1 The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. DM74AS646 • DM74AS648 Logic Diagrams positive logic DM74AS646 DM74AS648 Different Modes of Control for DM74AS646, DM74AS648

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DM74AS646
• DM74AS648 Octal Bus Transceiver and Register

DM74AS646
• DM74AS648 Octal Bus Transceiver and Register

This device incorporates an octal bus transceiver and an octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to bus.

This bus transceiver features totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide this device with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. It is particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The registers in the DM74AS646, DM74AS648 are edgetriggered D-type flip-flops. On the positive transition of the clock CAB or CBA , the input bus data is stored.

The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred. A LOW input level selects real-time data, and a HIGH level selects stored data. The select controls have a “make before break” configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between stored and real-time data.

The enable G and direction control pins provide four modes of operation real-time data transfer from bus A to B, realtime data transfer from bus B to A, real-time bus A and/or B data transfer to internal storage, or internal store data transfer to bus A or B.

When the enable G pin is LOW, the direction pin selects which bus receives data. When the enable G pin is HIGH, both buses become disabled yet their input function is still enabled.
s Switching specifications at 50 pF s Switching specifications guaranteed over full tempera-
ture and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL
process s Functionally and pin-for-pin compatible with LS TTL
counterpart s 3-STATE buffer-type outputs drive bus lines directly
Ordering Code:

Order Number Package Number

Package Description

DM74AS646WM

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide

DM74AS646NT

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

DM74AS648WM

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide

DM74AS648NT

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2003 Fairchild Semiconductor Corporation DS006324

DM74AS646
• DM74AS648

Connection Diagram

Function Table

Inputs

Data I/O Note 1

Operation or Function

G DIR CAB CBA SAB SBA A1 thru A8 B1 thru B8

DM74AS646

H X H or L H or L X

Input

Input Isolation, Hold Storage

Store A and B Data

DM74AS648 Isolation, Hold Storage Store A and B Data

X H or L X H

Output

Input

Real Time B Data to A Bus Real Time B Data to A Bus Stored B Data to A Bus Stored B Data to A Bus

Input

Output Real Time A Data to B Bus Real Time A Data to B Bus

H or L X H X

Stored A Data to B Bus Stored A Data to B Bus

Input Unspecified Store A, B Unspecified

Store A, B Unspecified

Note 1

Note 1

Note 1

X Unspecified Input Store B, A Unspecified

Store B, A Unspecified

Note 1

Note 1

Note 1
level transition

Note 1 The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.

DM74AS646
• DM74AS648

Logic Diagrams
positive logic

DM74AS646

DM74AS648

Different Modes of Control for DM74AS646, DM74AS648

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Datasheet ID: DM74AS648WM 513738