DM74AS574WMX

DM74AS574WMX Datasheet


DM74AS574 Octal D-Type Edge-Triggered Flip-Flops with 3-STATE Outputs

Part Datasheet
DM74AS574WMX DM74AS574WMX DM74AS574WMX (pdf)
Related Parts Information
DM74AS574N DM74AS574N DM74AS574N
DM74AS574WM DM74AS574WM DM74AS574WM
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DM74AS574 Octal D-Type Edge-Triggered Flip-Flops with 3-STATE Outputs

DM74AS574 Octal D-Type Edge-Triggered Flip-Flops with 3-STATE Outputs

These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased HIGH-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight flip-flops of the DM74AS574 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs.

A buffered output control input can be used to place the eight outputs in either a normal logic state HIGH or LOW logic levels or a high impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of the flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF.

The pinout is arranged to ease printed circuit board layout. All data inputs are on one side of the package while all the outputs are on the other side.
s Switching specifications at 50 pF s Switching specifications guaranteed over full tempera-
ture and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL
process s Functionally equivalent with DM74S374 s Improved AC performance over DM74S374 at approxi-
mately half the power s 3-STATE buffer-type outputs drive bus lines directly s Bus structured pinout
Ordering Code:

Order Number Package Number

Package Description

DM74AS574WM

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide

DM74AS574N

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram
2000 Fairchild Semiconductor Corporation DS006314

DM74AS574

Function Table

Output

Clock

Output

Control

L = LOW State H = HIGH State X = Don’t Care = Positive Edge Transition Z = High Impedance State Q0 = Previous Condition of Q

Logic Diagram

DM74AS574

Absolute Maximum Ratings Note 1

Supply Voltage

Input Voltage

Voltage Applied to Disabled Output
5.5V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range
−65°C to +150°C

Typical N Package
52.0°C/W

M Package
70.0°C/W

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

LOW Level Output Current
fCLK

Clock Frequency
tWCLK

Width of Clock Pulse

HIGH

Data Setup Time Note 2

Data Hold Time Note 2

Free Air Operating Temperature

Note 2 The arrow indicates the positive edge of the clock is used for reference.
More datasheets: F0424A | AS1720A-ATDT | AS1720B-ATDT | Z63000Z2910Z 1Z 2 | U99-C056-200T | 3540 | 53328-1576 | 53220-1572 | 884 | DM74AS574N


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Datasheet ID: DM74AS574WMX 513736