DM74ALS874BWMX

DM74ALS874BWMX Datasheet


DM74ALS874B Dual 4-Bit D-Type Edge-Triggered Flip-Flop with 3-STATE Outputs

Part Datasheet
DM74ALS874BWMX DM74ALS874BWMX DM74ALS874BWMX (pdf)
Related Parts Information
DM74ALS874BNT DM74ALS874BNT DM74ALS874BNT
DM74ALS874BWM DM74ALS874BWM DM74ALS874BWM
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DM74ALS874B Dual 4-Bit D-Type Edge-Triggered Flip-Flop with 3-STATE Outputs

DM74ALS874B Dual 4-Bit D-Type Edge-Triggered Flip-Flop with 3-STATE Outputs

This dual 4-bit register features totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic-level drive provide this register with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. It is particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight flip-flops of the DM74ALS874B are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs.

A buffered output control input can be used to place the eight outputs in either a normal logic state HIGH or LOW logic levels or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly.

The output control does not affect the internal operation of the flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are OFF.
s Switching specifications at 50 pF s Switching specifications guaranteed over full tempera-
ture and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL
process s 3-STATE buffer-type outputs drive bus lines directly s Space saving 300 mil wide package s Asynchronous clear
Ordering Code:

Order Number Package Number

Package Description

DM74ALS874BWM

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide

DM74ALS874BNT

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram
2001 Fairchild Semiconductor Corporation DS006244

DM74ALS874B

Function Table

Inputs

L = LOW State H = HIGH State X = Don’t Care = Positive Edge Transition Z = High Impedance State Q0 = Previous Condition of Q

CLK X L

Output

Logic Diagram

DM74ALS874B

Absolute Maximum Ratings Note 1

Supply Voltage Input Voltage Applied to Disabled Output Operating Free Air Temperature Range Storage Temperature Range Typical

N Package M Package
7V 5.5V 0°C to +70°C −65°C to +150°C
51.0°C/W 86.5°C/W

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Parameter

VCC VIH VIL IOH IOL fCLK tWCLK

Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency Width of Clock Pulse

HIGH LOW
tWCLR

Width of Clear Pulse

Data Setup Time Note 2

Data Hold Time Note 2

Clear Inactive

Free Air Operating Temperature

Note 2 The arrow indicates the positive edge of the Clock is used for reference.

Nom 5

Max 24 30

Units V mA

MHz ns °C

DM74ALS874B

Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C.

Parameter

Conditions

Input Clamp Voltage

HIGH Level

Output Voltage
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Datasheet ID: DM74ALS874BWMX 513705