DM74ALS74ASJ
DM74ALS74ASJ Datasheet
DM74ALS74A Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear
| Part | Datasheet |
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DM74ALS74ASJ |
DM74ALS74ASJ (pdf) |
| Related Parts | Information |
|---|---|
DM74ALS74AMX |
DM74ALS74AMX |
DM74ALS74ASJX |
DM74ALS74ASJX |
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DM74ALS74AM |
DM74ALS74AM |
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DM74ALS74AN |
DM74ALS74AN |
| PDF Datasheet Preview |
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| DM74ALS74A Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear DM74ALS74A Dual D Positive-Edge-Triggered Flip-Flop with Preset and Clear The DM74ALS74A contains two independent positive edge-triggered flip-flops. Each flip-flop has individual D, clock, clear and preset inputs, and also complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect. Asynchronous preset and clear inputs will set or clear Q output respectively upon the application of low level signal. s Switching specifications at 50 pF s Switching specifications guaranteed over full tempera- ture and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s Functionally and pin-for-pin compatible with Schottky and LS TTL counterpart s Improved AC performance over LS74 at approximately half the power Ordering Code: Order Number Package Number Package Description DM74ALS74AM M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow DM74ALS74ASJ M14D 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide DM74ALS74AN N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs PR CLR CLK D X H Note 1 H Note 1 L = LOW State H = HIGH State X = Don't Care = Positive Edge Transition Q0 = Previous Condition of Q Note 1 This condition is nonstable it will not persist when preset and clear inputs return to their inactive HIGH level. The output levels in this condition are not guaranteed to meet the VOH specification. 2000 Fairchild Semiconductor Corporation DS006109 DM74ALS74A Logic Diagram DM74ALS74A Absolute Maximum Ratings Note 2 Supply Voltage Input Voltage Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Typical N Package 87.0°C/W M Package 117.0°C/W Note 2 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Parameter VCC VIH VIL IOH IOL fCLK tW CLK Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency Width of Clock Pulse HIGH Pulse Width Preset & Clear Data Setup Time Data PRE or CLR Inactive Data Hold Time |
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