DM74ALS165M

DM74ALS165M Datasheet

DM74ALS165 8-Bit Parallel In/Serial Out Shift Register

Part	Datasheet
DM74ALS165M	DM74ALS165M (pdf)

Related Parts	Information
DM74ALS165MX	DM74ALS165MX

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DM74ALS165 8-Bit Parallel In/Serial Out Shift Register DM74ALS165 8-Bit Parallel In/Serial Out Shift Register May 2007 • Complementary outputs • Direct overriding load data inputs • Gated clock inputs • Parallel-to-serial data conversion The DM74ALS165 is an 8-bit serial register that, when clocked, shifts the data toward serial output, QH. Parallelin access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the SH/LD input. The DM74ALS165 also features a clock inhibit function and a complemented serial output, QH. Clocking is accomplished by a LOW-to-HIGH transition of the CLK input while SH/LD is held HIGH and CLK INH is held LOW. The functions of the CLK and CLK INH clock inhibit inputs are interchangeable. Since a LOW CLK input and a LOW-to-HIGH transition of CLK INH will also accomplish clocking, CLK INH should be changed to the high level only while the CLK input is HIGH. Parallel loading is inhibited when SH/LD is held HIGH. The parallel inputs to the register are enabled while SH/LD is LOW independently of the levels of CLK, CLK INH, or SER inputs. Ordering Information Order Number Package Number Package Description DM74ALS165M M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering number. Connection Diagram DM74ALS165 8-Bit Parallel In/Serial Out Shift Register Function Table Inputs Internal Outputs Shift/Load Clock Inhibit Clock X Serial Parallel A...H QA a...h Output QH H = HIGH Level steady-state L = LOW Level steady-state X = Don't Care any input, including transitions = Transition from LOW-to-HIGH level a...h = The level of steady-state input at inputs A through H, respectively QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established QAn, QGn = The level of QA or QG, respectively, before the most recent transition of the clock Logic Diagram 1986 Fairchild Semiconductor Corporation DM74ALS165 8-Bit Parallel In/Serial Out Shift Register Timing Diagram Typical Shift, Load, and Inhibit Sequences 1986 Fairchild Semiconductor Corporation DM74ALS165 8-Bit Parallel In/Serial Out Shift Register Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. VCC VI TA TSTG JA Parameter Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical Thermal Resistance Rating 7V 0°C to +70°C to +150°C 104.0°C/W Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VIH VIL IOH IOL fCLOCK tW tH TA Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency Pulse Duration CLK HIGH CLK LOW

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DM74ALS165 8-Bit Parallel In/Serial Out Shift Register

DM74ALS165 8-Bit Parallel In/Serial Out Shift Register

May 2007
• Complementary outputs
• Direct overriding load data inputs
• Gated clock inputs
• Parallel-to-serial data conversion

The DM74ALS165 is an 8-bit serial register that, when clocked, shifts the data toward serial output, QH. Parallelin access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the SH/LD input. The DM74ALS165 also features a clock inhibit function and a complemented serial output, QH.

Clocking is accomplished by a LOW-to-HIGH transition of the CLK input while SH/LD is held HIGH and CLK INH is held LOW. The functions of the CLK and CLK INH clock inhibit inputs are interchangeable. Since a LOW CLK input and a LOW-to-HIGH transition of CLK INH will also accomplish clocking, CLK INH should be changed to the high level only while the CLK input is HIGH. Parallel loading is inhibited when SH/LD is held HIGH. The parallel inputs to the register are enabled while SH/LD is LOW independently of the levels of CLK, CLK INH, or SER inputs.
Ordering Information

Order Number

Package Number

Package Description

DM74ALS165M

M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering number.

Connection Diagram

DM74ALS165 8-Bit Parallel In/Serial Out Shift Register

Function Table

Inputs

Internal Outputs

Shift/Load Clock Inhibit

Clock X

Serial Parallel A...H QA
a...h

Output QH

H = HIGH Level steady-state L = LOW Level steady-state X = Don't Care any input, including transitions = Transition from LOW-to-HIGH level a...h = The level of steady-state input at inputs A through H, respectively QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established

QAn, QGn = The level of QA or QG, respectively, before the most recent transition of the clock

Logic Diagram
1986 Fairchild Semiconductor Corporation

DM74ALS165 8-Bit Parallel In/Serial Out Shift Register

Timing Diagram

Typical Shift, Load, and Inhibit Sequences
1986 Fairchild Semiconductor Corporation

DM74ALS165 8-Bit Parallel In/Serial Out Shift Register

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

VCC VI TA TSTG JA

Parameter Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical Thermal Resistance

Rating 7V
0°C to +70°C to +150°C
104.0°C/W

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Symbol VCC VIH VIL IOH IOL
fCLOCK tW
tH TA

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

LOW Level Output Current

Clock Frequency

Pulse Duration CLK HIGH

CLK LOW

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Datasheet ID: DM74ALS165M 513661