DM7474N

DM7474N Datasheet

DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs

Part	Datasheet
DM7474N	DM7474N (pdf)

PDF Datasheet Preview
DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs This device contains two independent positive-edge-triggered D-type flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A LOW logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Ordering Code: Order Number Package Number Package Description DM7474M M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow DM7474N N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Outputs CLR CLK Note 1 Note 1 H = HIGH Logic Level X = Either LOW or HIGH Logic Level L = LOW Logic Level = Positive-going transition of the clock. Q0 = The output logic level of Q before the indicated input conditions were established. Note 1 This configuration is nonstable that is, it will not persist when either the preset and/or clear inputs return to their inactive HIGH level. 2001 Fairchild Semiconductor Corporation DS006526 DM7474 Absolute Maximum Ratings Note 2 Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0°C to +70°C −65°C to +150°C Note 2 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Parameter Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current fCLK Clock Frequency Note 4 Pulse Width Clock HIGH Note 4 Clock LOW 0 30 37 Clear LOW Preset LOW Input Setup Time Note 3 Note 4 Input Hold Time Note 3 Note 4 Free Air Operating Temperature Note 3 The symbol indicates the rising edge of the clock pulse is used for reference. Note 4 TA = 25°C and VCC = 5V. Nom 5 Max 16 15 Units V mA ns °C

PDF Datasheet Preview

DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs

DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs

This device contains two independent positive-edge-triggered D-type flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the
transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A LOW logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.
Ordering Code:

Order Number Package Number

Package Description

DM7474M

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

DM7474N

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

Outputs

CLR CLK

Note 1 Note 1

H = HIGH Logic Level X = Either LOW or HIGH Logic Level L = LOW Logic Level = Positive-going transition of the clock. Q0 = The output logic level of Q before the indicated input conditions were
established.

Note 1 This configuration is nonstable that is, it will not persist when either the preset and/or clear inputs return to their inactive HIGH level.
2001 Fairchild Semiconductor Corporation DS006526

DM7474

Absolute Maximum Ratings Note 2

Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range
7V 5.5V 0°C to +70°C −65°C to +150°C

Note 2 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Parameter

Supply Voltage

HIGH Level Input Voltage

LOW Level Input Voltage

HIGH Level Output Current

LOW Level Output Current
fCLK

Clock Frequency Note 4

Pulse Width

Clock HIGH

Note 4

Clock LOW
0 30 37

Clear LOW

Preset LOW

Input Setup Time Note 3 Note 4

Input Hold Time Note 3 Note 4

Free Air Operating Temperature

Note 3 The symbol indicates the rising edge of the clock pulse is used for reference.

Note 4 TA = 25°C and VCC = 5V.

Nom 5

Max 16 15

Units V mA
ns °C

More datasheets: KSH421J 50 LFS | KSH441J 50 LFS | KSH221J 50 LFS | KSH451J 50 LFS | 5571303203F | 2271-12-001 | 2274-12-021 | 2274-05-021 | 2271-05-001 | FJX4008RTF

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived DM7474N Datasheet file may be downloaded here without warranties.

Datasheet ID: DM7474N 513627